[coreboot-gerrit] Change in coreboot[master]: Move compiler.h to commonlib
Nico Huber (Code Review)
gerrit at coreboot.org
Thu Oct 4 23:49:31 CEST 2018
Nico Huber has uploaded a new patch set (#2). ( https://review.coreboot.org/28927 )
Change subject: Move compiler.h to commonlib
......................................................................
Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/arch/arm/include/arch/hlt.h
M src/arch/arm/stages.c
M src/arch/arm64/arm_tf.c
M src/arch/arm64/boot.c
M src/arch/arm64/include/arch/hlt.h
M src/arch/arm64/transition.c
M src/arch/mips/include/arch/hlt.h
M src/arch/power8/include/arch/hlt.h
M src/arch/riscv/include/arch/hlt.h
M src/arch/riscv/include/arch/io.h
M src/arch/x86/acpi.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/acpigen.c
M src/arch/x86/cbmem.c
M src/arch/x86/exception.c
M src/arch/x86/gdt.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/hlt.h
M src/arch/x86/include/arch/io.h
M src/arch/x86/include/arch/pci_io_cfg.h
M src/arch/x86/include/arch/pci_mmio_cfg.h
M src/arch/x86/include/arch/pirq_routing.h
M src/arch/x86/include/arch/registers.h
M src/arch/x86/include/arch/smp/atomic.h
M src/arch/x86/include/arch/smp/mpspec.h
M src/arch/x86/include/arch/smp/spinlock.h
M src/arch/x86/mpspec.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/postcar.c
M src/arch/x86/smbios.c
M src/arch/x86/timestamp.c
M src/commonlib/fsp_relocate.c
M src/commonlib/include/commonlib/cbfs_serialized.h
R src/commonlib/include/commonlib/compiler.h
M src/commonlib/include/commonlib/fmap_serialized.h
M src/commonlib/include/commonlib/rmodule-defs.h
M src/commonlib/include/commonlib/tcpa_log_serialized.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/commonlib/lz4_wrapper.c
M src/commonlib/storage/sdhci.c
M src/console/die.c
M src/console/post.c
M src/cpu/allwinner/a10/clock.h
M src/cpu/allwinner/a10/gpio.h
M src/cpu/allwinner/a10/timer.h
M src/cpu/allwinner/a10/uart.h
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/intel/microcode/microcode.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/cpu/ti/am335x/clock.h
M src/cpu/ti/am335x/gpio.h
M src/cpu/ti/am335x/header.c
M src/cpu/ti/am335x/header.h
M src/cpu/ti/am335x/uart.h
M src/cpu/x86/mp_init.c
M src/cpu/x86/pae/pgtbl.c
M src/cpu/x86/smm/smihandler.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/device.h
M src/device/oprom/yabel/pmm.h
M src/device/pci_rom.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/elog/boot_count.c
M src/drivers/elog/elog_internal.h
M src/drivers/elog/gsmi.c
M src/drivers/i2c/designware/dw_i2c.h
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_0/fsp_util.h
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/graphics.c
M src/drivers/intel/fsp2_0/hob_display.c
M src/drivers/intel/fsp2_0/include/fsp/upd.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/upd_display.c
M src/drivers/intel/gma/intel_bios.h
M src/drivers/intel/gma/opregion.h
M src/drivers/intel/mipi_camera/chip.h
M src/drivers/intel/wifi/wifi.c
M src/drivers/mrc_cache/mrc_cache.c
M src/drivers/siemens/nc_fpga/nc_fpga.h
M src/drivers/spi/spi-generic.c
M src/drivers/spi/tpm/tpm.c
M src/drivers/usb/ehci.h
M src/drivers/usb/usb_ch9.h
M src/drivers/vpd/vpd_tables.h
M src/ec/google/chromeec/crosec_proto.c
M src/include/console/console.h
M src/include/console/spi.h
M src/include/cpu/amd/mtrr.h
M src/include/cpu/x86/cache.h
M src/include/cpu/x86/cr.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
M src/include/cpu/x86/smm.h
M src/include/device/pci_ops.h
M src/include/elog.h
M src/include/halt.h
M src/include/memory_info.h
M src/include/reset.h
M src/include/sar.h
M src/include/smbios.h
M src/include/vbe.h
M src/lib/boot_device.c
M src/lib/bootblock.c
M src/lib/cbfs.c
M src/lib/cbmem_common.c
M src/lib/cbmem_console.c
M src/lib/coreboot_table.c
M src/lib/fallback_boot.c
M src/lib/gpio.c
M src/lib/hardwaremain.c
M src/lib/imd.c
M src/lib/imd_cbmem.c
M src/lib/prog_loaders.c
M src/lib/prog_ops.c
M src/lib/reset.c
M src/lib/timer.c
M src/lib/timestamp.c
M src/lib/wrdd.c
M src/mainboard/emulation/qemu-i440fx/fw_cfg.c
M src/mainboard/google/cyan/romstage.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/google/kahlee/mainboard.c
M src/mainboard/google/kahlee/romstage.c
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/kahlee/variants/baseboard/memory.c
M src/mainboard/google/octopus/mainboard.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/octopus/variants/baseboard/memory.c
M src/mainboard/google/octopus/variants/baseboard/nhlt.c
M src/mainboard/google/poppy/ramstage.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/poppy/variants/baseboard/memory.c
M src/mainboard/google/poppy/variants/baseboard/nhlt.c
M src/mainboard/google/poppy/variants/nami/mainboard.c
M src/mainboard/google/reef/mainboard.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/baseboard/memory.c
M src/mainboard/google/reef/variants/baseboard/nhlt.c
M src/mainboard/google/zoombini/memory.c
M src/mainboard/google/zoombini/variants/baseboard/gpio.c
M src/mainboard/google/zoombini/variants/baseboard/nhlt.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/coffeelake_rvp/memory.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/memory.c
M src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
M src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/include/variant/ptn3460.h
M src/mainboard/siemens/mc_tcu3/ptn3460.h
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdmct/mct/mct_d.h
M src/northbridge/amd/lx/raminit.c
M src/northbridge/amd/pi/agesawrapper.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/pei_data.h
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/nehalem/raminit.c
M src/northbridge/intel/sandybridge/pei_data.h
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/security/tpm/tss/tcg-2.0/tss_structures.h
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_logic.c
M src/security/vboot/verstage.c
M src/soc/amd/common/block/include/amdblocks/psp.h
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/common/block/pi/def_callouts.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/gpio.c
M src/soc/amd/stoneyridge/include/soc/nvs.h
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cse.c
M src/soc/intel/apollolake/include/soc/nvs.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/baytrail/gpio.c
M src/soc/intel/baytrail/include/soc/device_nvs.h
M src/soc/intel/baytrail/include/soc/efi_wrapper.h
M src/soc/intel/baytrail/include/soc/gpio.h
M src/soc/intel/baytrail/include/soc/mrc_wrapper.h
M src/soc/intel/baytrail/include/soc/nvs.h
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/gpio.c
M src/soc/intel/braswell/include/soc/device_nvs.h
M src/soc/intel/braswell/include/soc/gpio.h
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/braswell/include/soc/pm.h
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/include/soc/device_nvs.h
M src/soc/intel/broadwell/include/soc/gpio.h
M src/soc/intel/broadwell/include/soc/me.h
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/broadwell/include/soc/pei_data.h
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/nvs.h
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/reset.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/acpi_wake_source.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/ebda/ebda.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/rtc/rtc.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/common/mma.c
M src/soc/intel/common/vbt.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/fiamux.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/fsp_baytrail/gpio.c
M src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
M src/soc/intel/fsp_baytrail/include/soc/gpio.h
M src/soc/intel/fsp_baytrail/include/soc/nvs.h
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/include/soc/gpio.h
M src/soc/intel/fsp_broadwell_de/include/soc/smm.h
M src/soc/intel/fsp_broadwell_de/spi.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/include/soc/pei_wrapper.h
M src/soc/intel/quark/include/soc/pm.h
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/soc/device_nvs.h
M src/soc/intel/skylake/include/soc/me.h
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/skylake/include/soc/pei_data.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/mediatek/common/mmu_operations.c
M src/soc/mediatek/common/timer.c
M src/soc/mediatek/common/uart.c
M src/soc/nvidia/tegra124/include/soc/clk_rst.h
M src/soc/nvidia/tegra124/include/soc/dma.h
M src/soc/nvidia/tegra124/include/soc/emc.h
M src/soc/nvidia/tegra124/include/soc/spi.h
M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
M src/soc/nvidia/tegra124/uart.c
M src/soc/nvidia/tegra210/bootblock.c
M src/soc/nvidia/tegra210/funitcfg.c
M src/soc/nvidia/tegra210/include/soc/clk_rst.h
M src/soc/nvidia/tegra210/include/soc/clst_clk.h
M src/soc/nvidia/tegra210/include/soc/dma.h
M src/soc/nvidia/tegra210/include/soc/emc.h
M src/soc/nvidia/tegra210/include/soc/spi.h
M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
M src/soc/nvidia/tegra210/romstage.c
M src/soc/nvidia/tegra210/uart.c
M src/soc/qualcomm/ipq40xx/include/soc/cdp.h
M src/soc/qualcomm/ipq40xx/lcc.c
M src/soc/qualcomm/ipq806x/include/soc/cdp.h
M src/soc/qualcomm/ipq806x/lcc.c
M src/soc/samsung/exynos5250/i2c.c
M src/soc/samsung/exynos5250/include/soc/power.h
M src/soc/samsung/exynos5420/i2c.c
M src/soc/samsung/exynos5420/include/soc/dmc.h
M src/soc/samsung/exynos5420/include/soc/power.h
M src/southbridge/amd/sb700/sata.c
M src/southbridge/intel/bd82x6x/me.h
M src/southbridge/intel/bd82x6x/nvs.h
M src/southbridge/intel/common/gpio.h
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/fsp_bd82x6x/gpio.h
M src/southbridge/intel/fsp_bd82x6x/me.h
M src/southbridge/intel/fsp_bd82x6x/nvs.h
M src/southbridge/intel/fsp_i89xx/gpio.h
M src/southbridge/intel/fsp_i89xx/me.h
M src/southbridge/intel/fsp_i89xx/nvs.h
M src/southbridge/intel/fsp_rangeley/gpio.h
M src/southbridge/intel/fsp_rangeley/nvs.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82801dx/nvs.h
M src/southbridge/intel/i82801gx/nvs.h
M src/southbridge/intel/i82801ix/nvs.h
M src/southbridge/intel/i82801jx/nvs.h
M src/southbridge/intel/ibexpeak/me.h
M src/southbridge/intel/ibexpeak/nvs.h
M src/southbridge/intel/lynxpoint/lp_gpio.h
M src/southbridge/intel/lynxpoint/me.h
M src/southbridge/intel/lynxpoint/nvs.h
M src/southbridge/ricoh/rl5c476/rl5c476.h
M src/vendorcode/google/chromeos/gnvs.h
M util/cbfstool/Makefile.inc
M util/cbfstool/cbfs.h
D util/cbfstool/compiler.h
M util/cbfstool/fit.c
M util/cbfstool/flashmap/fmap.h
M util/cbfstool/ifwitool.c
D util/cbmem/compiler.h
336 files changed, 354 insertions(+), 408 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/28927/2
--
To view, visit https://review.coreboot.org/28927
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Gerrit-Change-Number: 28927
Gerrit-PatchSet: 2
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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