[coreboot-gerrit] Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
Name of user not set (Code Review)
gerrit at coreboot.org
Fri Nov 30 15:05:08 CET 2018
nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29981
Change subject: qcs405: Add bl31 stage and elf
......................................................................
qcs405: Add bl31 stage and elf
Change-Id: I967c0b78a3561574609bf8332a22838c85e43429
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
---
M src/arch/arm64/Makefile.inc
M src/soc/qualcomm/qcs405/Kconfig
M src/soc/qualcomm/qcs405/Makefile.inc
A src/soc/qualcomm/qcs405/bl31_plat_params.c
A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
M src/soc/qualcomm/qcs405/include/soc/symbols.h
7 files changed, 124 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/1
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index 6bb7196..bf2f01b 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -157,6 +157,8 @@
ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y)
+ifneq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
+
ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"")
BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware
@@ -235,6 +237,8 @@
endif # CONFIG_ARM64_USE_SECURE_OS
+endif # CONFIG_SOC_QUALCOMM_QCS405
+
endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE
endif # CONFIG_ARCH_RAMSTAGE_ARM64
diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
index 29960d4..6704d79 100644
--- a/src/soc/qualcomm/qcs405/Kconfig
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -6,6 +6,7 @@
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
+ select ARM64_USE_ARM_TRUSTED_FIRMWARE
select BOOTBLOCK_CONSOLE
select GENERIC_GPIO_LIB
select GENERIC_UDELAY
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index 40dcb9b..a5f9779 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -41,6 +41,7 @@
ramstage-y += rpm_load_reset.c
ramstage-y += usb.c
ramstage-y += flash_controller.c
+ramstage-y += bl31_plat_params.c
################################################################################
@@ -86,6 +87,18 @@
endif
################################################################################
+
+BL31_FILE := $(QCS405_BLOB)/bl31.elf
+bl31_file := $(shell ls $(BL31_FILE))
+ifneq (,$(findstring $(BL31_FILE),$(bl31_file)))
+ BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31
+ $(BL31_CBFS)-file := $(BL31_FILE)
+ $(BL31_CBFS)-type := payload
+ $(BL31_CBFS)-compression := none
+ cbfs-files-y += $(BL31_CBFS)
+endif
+################################################################################
+
QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn
qc_sec_file := $(shell ls $(QC_SEC_FILE))
ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file)))
diff --git a/src/soc/qualcomm/qcs405/bl31_plat_params.c b/src/soc/qualcomm/qcs405/bl31_plat_params.c
new file mode 100644
index 0000000..68a3c14
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/bl31_plat_params.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Qualcomm Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arm_tf.h>
+#include <assert.h>
+#include <cbmem.h>
+#include <soc/bl31_plat_params.h>
+
+static struct bl31_plat_param *plat_params;
+
+void register_bl31_param(struct bl31_plat_param *param)
+{
+ param->next = plat_params;
+ plat_params = param;
+}
+
+void *soc_get_bl31_plat_params(bl31_params_t *bl31_params)
+{
+ static struct bl31_u64_param cbtable_param = {
+ .h = { .type = PARAM_COREBOOT_TABLE, },
+ };
+ if (!cbtable_param.value) {
+ cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE);
+ if (cbtable_param.value)
+ register_bl31_param(&cbtable_param.h);
+ }
+ return plat_params;
+}
diff --git a/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h
new file mode 100644
index 0000000..d7a8e28
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Qualcomm Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BL31_PLAT_PARAMS_H__
+#define __BL31_PLAT_PARAMS_H__
+
+#if 0
+#include <arm-trusted-firmware/plat/qti/common/inc/qti_plat_params.h>
+#else
+/* param type */
+enum {
+ PARAM_NONE = 0,
+ PARAM_COREBOOT_TABLE,
+};
+
+/* common header for all plat parameter type */
+struct bl31_plat_param {
+ uint64_t type;
+ void *next;
+};
+
+struct bl31_u64_param {
+ struct bl31_plat_param h;
+ uint64_t value;
+};
+#endif
+
+void register_bl31_param(struct bl31_plat_param *param);
+
+#endif/* __BL31_PLAT_PARAMS_H__ */
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index 9e7df11..46d4673 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -51,6 +51,7 @@
REGION(qclib, 0x8C6a000, 0x80000, 4096)
//REGION(dcb, 0x8CEa000, 0x4000, 4096)
REGION(pmic, 0x8CED000, 0x10000, 4096)
+ REGION(el3_stack_canary, 0x8CFD000, 0x8, 0x10)
BSRAM_END(0x8D80000)
DRAM_START(0x80000000)
diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h
index 74ba170..28b93f9 100644
--- a/src/soc/qualcomm/qcs405/include/soc/symbols.h
+++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_
-#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_
+#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_
#include <types.h>
@@ -42,4 +42,24 @@
extern u8 _erpm[];
#define _rpm_size (_erpm - _rpm)
-#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+extern u8 _el3_stack_canary[];
+extern u8 _eel3_stack_canary[];
+#define _el3_stack_canary_size (_eel3_stack_canary - _el3_stack_canary)
+
+extern u8 _ddr_training[];
+extern u8 _eddr_training[];
+#define _ddr_training_size (_eddr_training - _ddr_training)
+
+extern u8 _qclib_serial_log[];
+extern u8 _eqclib_serial_log[];
+#define _qclib_serial_log_size (_eqclib_serial_log - _qclib_serial_log)
+
+extern u8 _limits_cfg[];
+extern u8 _elimits_cfg[];
+#define _limits_cfg_size (_elimits_cfg - _limits_cfg)
+
+extern u8 _ddr_information[];
+extern u8 _eddr_information[];
+#define _ddr_information_size (_eddr_information - _ddr_information)
+
+#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_
--
To view, visit https://review.coreboot.org/c/coreboot/+/29981
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429
Gerrit-Change-Number: 29981
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-MessageType: newchange
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181130/a5362bbc/attachment-0001.html>
More information about the coreboot-gerrit
mailing list