[coreboot-gerrit] Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned

[Name of user not set (Code Review)]

nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29969


Change subject: qcs405: memlayout: Make bootblock 64k aligned
......................................................................

qcs405: memlayout: Make bootblock 64k aligned

The qc_sec in qcs405 excepts that bootblock to be 64k aligned. So
adjust the memlayout accordingly.

Change-Id: I1599242bb5158477318867508c72dc14f1244b00
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
---
M src/arch/arm64/armv8/bootblock.S
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
2 files changed, 15 insertions(+), 13 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/1

diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S
index e5758bc..7dc8b0f 100644
--- a/src/arch/arm64/armv8/bootblock.S
+++ b/src/arch/arm64/armv8/bootblock.S
@@ -23,7 +23,9 @@
 
 ENTRY(_start)
 	/* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */
-	bl	arm64_init_cpu
+	ldr x15, =arm64_init_cpu
+	blr x15
 
-	bl	main
+	ldr x15, =main
+	blr x15
 ENDPROC(_start)
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index dadbbe8..8566f9f 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -31,17 +31,17 @@
 
 	BSRAM_START(0x8C00000)
 	REGION(fw_reserved2, 0x8C00000, 0x16000, 4096)
-	OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K)
-	BOOTBLOCK(0x8C2F000, 40K)
-	TTB(0x8C39000, 56K)
-	VBOOT2_WORK(0x8C47000, 16K)
-	STACK(0x8C4B000, 16K)
-	TIMESTAMP(0x8C4F000, 1K)
-	PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
-	PRERAM_CBFS_CACHE(0x8C57400, 70K)
-	//REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
-	REGION(qclib, 0x8C69000, 0x80000, 4096)
-	REGION(dcb, 0x8CE9000, 0x4000, 4096)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 104K)
+	BOOTBLOCK(0x8C30000, 40K)
+	TTB(0x8C3a000, 56K)
+	VBOOT2_WORK(0x8C48000, 16K)
+	STACK(0x8C4c000, 16K)
+	TIMESTAMP(0x8C50000, 1K)
+	PRERAM_CBMEM_CONSOLE(0x8C50400, 32K)
+	PRERAM_CBFS_CACHE(0x8C58400, 70K)
+	//REGION(bsram_unused, 0x8C69C00, 0xA2400, 0x100)
+	REGION(qclib, 0x8C6a000, 0x80000, 4096)
+	//REGION(dcb, 0x8CEa000, 0x4000, 4096)
 	REGION(pmic, 0x8CED000, 0x10000, 4096)
 	BSRAM_END(0x8D80000)
 

-- 
To view, visit https://review.coreboot.org/c/coreboot/+/29969
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00
Gerrit-Change-Number: 29969
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: nsekar at codeaurora.org
Gerrit-MessageType: newchange
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181130/11a243e5/attachment-0001.html>