[coreboot-gerrit] Change in ...coreboot[master]: qcs405: Adding the GPIO support for QCS405
Name of user not set (Code Review)
gerrit at coreboot.org
Fri Nov 30 11:14:05 CET 2018
nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29963
Change subject: qcs405: Adding the GPIO support for QCS405
......................................................................
qcs405: Adding the GPIO support for QCS405
Add the gpio data for all qcs405 pins
Change-Id: Ibdd675527458e597c1f49544425146bd17f28075
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
Signed-off-by: Pranav Agrawal <pranava at codeaurora.org>
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
---
M src/soc/qualcomm/qcs405/include/soc/gpio.h
1 file changed, 184 insertions(+), 218 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29963/1
diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h
index f436595..b12ebb1 100644
--- a/src/soc/qualcomm/qcs405/include/soc/gpio.h
+++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h
@@ -98,247 +98,213 @@
GPIO##index##_FUNC_##func7 = 7
enum {
- PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5,
- RES_6, RES_7),
+ PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5,
+ PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5,
RES_6, RES_7),
- PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5,
+ PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
RES_6, RES_7),
- PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4,
+ PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N,
RES_5, RES_6, RES_7),
- PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4,
+ PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5,
+ RES_6, RES_7),
+ PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4,
RES_5, RES_6, RES_7),
- PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4,
+ PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4,
RES_5, RES_6, RES_7),
- PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4,
+ PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4,
RES_5, RES_6, RES_7),
- PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3,
+ PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A,
RES_4, RES_5, RES_6, RES_7),
- PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5,
- RES_6, RES_7),
- PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0,
- MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT),
- PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK,
- RES_5, RES_6, RES_7),
- PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB,
+ PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A,
RES_4, RES_5, RES_6, RES_7),
- PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3,
+ PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5,
+ RES_6, RES_7),
+ PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5,
+ RES_6, RES_7),
+ PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6,
+ RES_7),
+ PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT,
RES_4, RES_5, RES_6, RES_7),
- PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5,
+ PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
RES_6, RES_7),
- PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3,
+ PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N,
RES_4, RES_5, RES_6, RES_7),
- PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE,
+ PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4,
RES_5, RES_6, RES_7),
- PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF,
+ PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4,
RES_5, RES_6, RES_7),
- PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4,
+ PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4,
RES_5, RES_6, RES_7),
- PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4,
+ PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4,
RES_5, RES_6, RES_7),
- PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5,
+ PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6,
+ RES_7),
+ PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5,
RES_6, RES_7),
- PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5,
+ PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5,
RES_6, RES_7),
- PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4,
+ PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6,
+ RES_7),
+ PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5,
+ RES_6, RES_7),
+ PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4,
RES_5, RES_6, RES_7),
- PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD,
+ PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4,
RES_5, RES_6, RES_7),
- PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
+ PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
};
struct tlmm_gpio {
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibdd675527458e597c1f49544425146bd17f28075
Gerrit-Change-Number: 29963
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-MessageType: newchange
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