[coreboot-gerrit] Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
Name of user not set (Code Review)
gerrit at coreboot.org
Fri Nov 30 11:14:03 CET 2018
nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29959
Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405
......................................................................
qcs405:Add SPI_RAM_SIMULATION support for QCS405
Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
---
M src/mainboard/google/mistral/romstage.c
M src/soc/qualcomm/qcs405/Kconfig
M src/soc/qualcomm/qcs405/Makefile.inc
A src/soc/qualcomm/qcs405/flash_controller.c
A src/soc/qualcomm/qcs405/include/soc/flash_controller.h
M src/soc/qualcomm/qcs405/include/soc/mmu.h
M src/soc/qualcomm/qcs405/mmu.c
M src/soc/qualcomm/qcs405/spi.c
8 files changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29959/1
diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c
index 079e20b..71968fc 100644
--- a/src/mainboard/google/mistral/romstage.c
+++ b/src/mainboard/google/mistral/romstage.c
@@ -21,6 +21,12 @@
#include <timestamp.h>
#include <arch/stages.h>
+#ifdef CONFIG_QC_SOC_SIMULATE
+extern void qcs405_mmu_dram_config_c(void);
+#endif
void platform_romstage_main(void)
{
+#ifdef CONFIG_QC_SOC_SIMULATE
+ qcs405_mmu_dram_config_c();
+#endif
}
diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
index 492e80e..b24dc9e 100644
--- a/src/soc/qualcomm/qcs405/Kconfig
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -20,4 +20,10 @@
select VBOOT_RETURN_FROM_VERSTAGE
select VBOOT_OPROM_MATTERS
select VBOOT_STARTS_IN_BOOTBLOCK
+
+config QC_SOC_SIMULATE
+ bool
+ prompt "Build for Early Simulation Environment"
+ default y
+
endif
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index 158ce34..17ba0f1 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -8,17 +8,20 @@
bootblock-y += timer.c
bootblock-y += gpio.c
bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
+bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c
################################################################################
verstage-y += spi.c
verstage-y += timer.c
verstage-y += gpio.c
+verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c
################################################################################
romstage-y += spi.c
romstage-y += cbmem.c
romstage-y += timer.c
romstage-y += gpio.c
+romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c
################################################################################
ramstage-y += soc.c
@@ -26,6 +29,7 @@
ramstage-y += cbmem.c
ramstage-y += timer.c
ramstage-y += gpio.c
+ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c
################################################################################
diff --git a/src/soc/qualcomm/qcs405/flash_controller.c b/src/soc/qualcomm/qcs405/flash_controller.c
new file mode 100644
index 0000000..1cb2aeb
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/flash_controller.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Qualcomm Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <symbols.h>
+#include <timer.h>
+
+static struct spi_flash *ram_flash;
+static struct spi_ctrlr *ram_ctrlr;
+
+#define ROM_BASE 0xA0000000 /* Above cbmem_top() */
+
+int spi_simulate_ram_flash_probe(const struct spi_slave *spi,
+ struct spi_flash *flash);
+
+static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf)
+{
+ void *ap = (void *)ROM_BASE;
+ ap += addr;
+ memcpy(buf, ap, len);
+ return 0;
+}
+
+static int ram_write(const struct spi_flash *flash, u32 addr, size_t len,
+ const void *buf)
+{
+ void *ap = (void *)ROM_BASE;
+ ap += addr;
+ memcpy(ap, buf, len);
+ return 0;
+}
+
+static int ram_erase(const struct spi_flash *flash, u32 offset, size_t len)
+{
+ void *ap = (void *)ROM_BASE;
+ ap += offset;
+ memset(ap, 0xFF, len);
+ return 0;
+}
+
+static int ram_status(const struct spi_flash *flash, u8 *reg)
+{
+ return 0;
+}
+
+static struct spi_flash_ops ram_ops =
+{
+ .read = ram_read,
+ .write = ram_write,
+ .erase = ram_erase,
+ .status = ram_status,
+};
+
+int spi_simulate_ram_flash_probe(const struct spi_slave *spi,
+ struct spi_flash *flash)
+{
+ static char name[] = "ram_flash";
+
+ printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__);
+
+ printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__);
+
+ ram_flash = flash;
+ ram_ctrlr = (struct spi_ctrlr *)spi->ctrlr;
+ ram_ctrlr->max_xfer_size = 0x10000;
+ flash->spi.bus = spi->bus;
+ flash->spi.cs = spi->cs;
+ flash->spi.ctrlr = ram_ctrlr;
+ flash->name = name;
+ flash->size = 0x800000;
+ flash->sector_size = 0x200;
+ flash->erase_cmd = 0x10;
+ flash->status_cmd = 0x20;
+ flash->ops = &ram_ops;
+
+ return 0;
+}
diff --git a/src/soc/qualcomm/qcs405/include/soc/flash_controller.h b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h
new file mode 100644
index 0000000..0641928
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Qualcomm Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__
+#define __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__
+
+#include <cbfs.h>
+#include <spi-generic.h>
+#include <stdint.h>
+
+struct spi_flash *qcs405_nor_flash_probe(struct spi_slave *spi);
+#endif /* __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ */
diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h
index 75cb320..3951f96 100644
--- a/src/soc/qualcomm/qcs405/include/soc/mmu.h
+++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h
@@ -19,5 +19,8 @@
#define DRAMSIZE4GB 0x100000000
void qcs405_mmu_init(void);
+#ifdef CONFIG_QC_SOC_SIMULATE
+void qcs405_mmu_dram_config_c(void);
+#endif
#endif // _SOC_QUALCOMM_QCS405_MMU_H_
diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c
index b47de42..bebca24 100644
--- a/src/soc/qualcomm/qcs405/mmu.c
+++ b/src/soc/qualcomm/qcs405/mmu.c
@@ -27,6 +27,16 @@
MA_DEV | MA_S | MA_RW);
mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW);
mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW);
+#ifdef CONFIG_QC_SOC_SIMULATE
+ mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW);
+#endif
mmu_enable();
}
+
+#ifdef CONFIG_QC_SOC_SIMULATE
+void qcs405_mmu_dram_config_c(void)
+{
+ mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW);
+}
+#endif
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
index c04b15d..73e538e 100644
--- a/src/soc/qualcomm/qcs405/spi.c
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -16,6 +16,25 @@
#include <spi-generic.h>
#include <spi_flash.h>
+#if IS_ENABLED(CONFIG_QC_SOC_SIMULATE)
+
+extern int spi_simulate_ram_flash_probe(const struct spi_slave *spi,
+ struct spi_flash *flash);
+
+static const struct spi_ctrlr spi_ctrlr = {
+ .flash_probe = spi_simulate_ram_flash_probe,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+ {
+ .ctrlr = &spi_ctrlr,
+ .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+ .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+ }
+};
+
+#else
+
static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
{
return 0;
@@ -47,4 +66,6 @@
},
};
+#endif
+
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe
Gerrit-Change-Number: 29959
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: nsekar at codeaurora.org
Gerrit-MessageType: newchange
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