[coreboot-gerrit] Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support

[Name of user not set (Code Review)]

nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29950


Change subject: soc/qualcomm/qcs405: Add MMU support
......................................................................

soc/qualcomm/qcs405: Add MMU support

Initialize 1st 4GB as Device Memory, except:
 * 1st page: NULL address
 * System_IMEM: Cached SRAM
 * Boot_IMEM: Cached SRAM

Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/bootblock.c
A src/soc/qualcomm/qcs405/include/soc/mmu.h
A src/soc/qualcomm/qcs405/include/soc/symbols.h
A src/soc/qualcomm/qcs405/mmu.c
5 files changed, 85 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29950/1

diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index 15f5a0c..2d1f842 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -5,6 +5,7 @@
 bootblock-y += bootblock.c
 bootblock-y += timer.c
 bootblock-y += spi.c
+bootblock-y += mmu.c
 
 ################################################################################
 verstage-y += timer.c
diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c
index 3ed37ae..5e63f13 100644
--- a/src/soc/qualcomm/qcs405/bootblock.c
+++ b/src/soc/qualcomm/qcs405/bootblock.c
@@ -14,8 +14,9 @@
  */
 
 #include <bootblock_common.h>
+#include <soc/mmu.h>
 
 void bootblock_soc_init(void)
 {
-
+	qcs405_mmu_init();
 }
diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h
new file mode 100644
index 0000000..bc42e72
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_MMU_H__
+#define _SOC_QUALCOMM_QCS405_MMU_H__
+
+void qcs405_mmu_init(void);
+
+#endif  // _SOC_QUALCOMM_QCS405_MMU_H_
diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h
new file mode 100644
index 0000000..7b35c55
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+
+#include <types.h>
+
+extern u8 _ssram[];
+extern u8 _essram[];
+#define _ssram_size (_essram - _ssram)
+
+extern u8 _bsram[];
+extern u8 _ebsram[];
+#define _bsram_size (_ebsram - _bsram)
+
+#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_
diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c
new file mode 100644
index 0000000..b47de42
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/mmu.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/symbols.h>
+
+void qcs405_mmu_init()
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)),
+			MA_DEV | MA_S | MA_RW);
+	mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW);
+	mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW);
+
+	mmu_enable();
+}

-- 
To view, visit https://review.coreboot.org/c/coreboot/+/29950
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Gerrit-Change-Number: 29950
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-MessageType: newchange
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181130/3dd1fe7c/attachment-0001.html>