[coreboot-gerrit] Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
Name of user not set (Code Review)
gerrit at coreboot.org
Fri Nov 30 11:13:57 CET 2018
nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29948
Change subject: soc/qualcomm/qcs405: Support for new SoC
......................................................................
soc/qualcomm/qcs405: Support for new SoC
Adding the basic infrastruture soc support for qcs405 and
a new build variant.
TEST=build
Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
---
A src/soc/qualcomm/qcs405/Kconfig
A src/soc/qualcomm/qcs405/Makefile.inc
A src/soc/qualcomm/qcs405/bootblock.c
A src/soc/qualcomm/qcs405/cbmem.c
A src/soc/qualcomm/qcs405/include/soc/gpio.h
A src/soc/qualcomm/qcs405/include/soc/memlayout.ld
A src/soc/qualcomm/qcs405/soc.c
A src/soc/qualcomm/qcs405/spi.c
A src/soc/qualcomm/qcs405/timer.c
9 files changed, 288 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29948/1
diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
new file mode 100644
index 0000000..560d988
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -0,0 +1,21 @@
+
+config SOC_QUALCOMM_QCS405
+ bool
+ default n
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select BOOTBLOCK_CONSOLE
+ select GENERIC_GPIO_LIB
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+
+if SOC_QUALCOMM_QCS405
+
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_RETURN_FROM_VERSTAGE
+ select VBOOT_OPROM_MATTERS
+ select VBOOT_STARTS_IN_BOOTBLOCK
+endif
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
new file mode 100644
index 0000000..15f5a0c
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -0,0 +1,32 @@
+
+ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += timer.c
+bootblock-y += spi.c
+
+################################################################################
+verstage-y += timer.c
+verstage-y += spi.c
+
+################################################################################
+romstage-y += timer.c
+romstage-y += spi.c
+romstage-y += cbmem.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += timer.c
+ramstage-y += spi.c
+ramstage-y += cbmem.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+ @printf "Generating: $(subst $(obj)/,,$(@))\n"
+ cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+
+endif
diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c
new file mode 100644
index 0000000..3ed37ae
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/bootblock.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+
+void bootblock_soc_init(void)
+{
+
+}
diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c
new file mode 100644
index 0000000..3b9ad4a
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/cbmem.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ return (void *)((uintptr_t)4 * GiB);
+}
diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h
new file mode 100644
index 0000000..e1ad453
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_GPIO_H_
+#define _SOC_QUALCOMM_QCS405_GPIO_H_
+
+#include <types.h>
+
+typedef u32 gpio_t;
+
+#endif // _SOC_QUALCOMM_QCS405_GPIO_H_
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
new file mode 100644
index 0000000..c0f5759
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
+#define SSRAM_START(addr) SYMBOL(ssram, addr)
+#define SSRAM_END(addr) SYMBOL(essram, addr)
+
+/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */
+#define BSRAM_START(addr) SYMBOL(bsram, addr)
+#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+
+SECTIONS
+{
+ SSRAM_START(0x8600000)
+ SSRAM_END(0x8608000)
+
+ BSRAM_START(0x8C00000)
+ OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K)
+ REGION(fw_reserved2, 0x8C19000, 0x16000, 4096)
+ BOOTBLOCK(0x8C2F000, 40K)
+ TTB(0x8C39000, 56K)
+ VBOOT2_WORK(0x8C47000, 16K)
+ STACK(0x8C4B000, 16K)
+ TIMESTAMP(0x8C4F000, 1K)
+ PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
+ PRERAM_CBFS_CACHE(0x8C57400, 70K)
+ REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
+/* REGION(qclib, 0x8D0B000, 0x80000, 4096)
+ REGION(dcb, 0x8D8B000, 0x4000, 4096)
+ REGION(pmic, 0x8D8F000, 0xA000, 4096)*/
+ BSRAM_END(0x8D80000)
+
+ DRAM_START(0x90000000)
+ POSTRAM_CBFS_CACHE(0x90000000, 384K)
+ RAMSTAGE(0x90800000, 128K)
+}
diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c
new file mode 100644
index 0000000..7870219
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/soc.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <timestamp.h>
+
+static void soc_read_resources(device_t dev)
+{
+
+}
+
+static void soc_init(device_t dev)
+{
+
+}
+
+static struct device_operations soc_ops = {
+ .read_resources = soc_read_resources,
+ .init = soc_init,
+};
+
+static void enable_soc_dev(device_t dev)
+{
+ dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_qcs405_ops = {
+ CHIP_NAME("SOC Qualcomm QCS405")
+ .enable_dev = enable_soc_dev,
+};
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
new file mode 100644
index 0000000..c04b15d
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
+{
+ return 0;
+}
+
+static void spi_ctrlr_release_bus(const struct spi_slave *slave)
+{
+
+}
+
+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
+ size_t bytes_out, void *din, size_t bytes_in)
+{
+ return 0;
+}
+
+static const struct spi_ctrlr spi_ctrlr = {
+ .claim_bus = spi_ctrlr_claim_bus,
+ .release_bus = spi_ctrlr_release_bus,
+ .xfer = spi_ctrlr_xfer,
+ .max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+ {
+ .ctrlr = &spi_ctrlr,
+ .bus_start = 0,
+ .bus_end = 0,
+ },
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c
new file mode 100644
index 0000000..8fb84c8
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/timer.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <timer.h>
+#include <delay.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+
+}
+
+void init_timer(void)
+{
+
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Gerrit-Change-Number: 29948
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-MessageType: newchange
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