[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common: Limit BIOS region cache to 16MB

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29944


Change subject: soc/intel/common: Limit BIOS region cache to 16MB
......................................................................

soc/intel/common: Limit BIOS region cache to 16MB

Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1, FLASH+APIC LT will be less than
20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries.

BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.

Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 4 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29944/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 5ff0872..8649f0c 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -240,6 +240,10 @@
 	if (!bios_size)
 		return;
 
+	/* Cache up to 16MB to boost boot performace */
+	if (bios_size > 16 * MiB)
+		bios_size = 16 * MiB;
+
 	/* Round to power of two */
 	alignment = 1UL << (log2_ceil(bios_size));
 	bios_size = ALIGN_UP(bios_size, alignment);

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Gerrit-Change-Number: 29944
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-MessageType: newchange
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