[coreboot-gerrit] Change in ...coreboot[master]: Untangle CBFS microcode updates
Nico Huber (Code Review)
gerrit at coreboot.org
Thu Nov 29 17:06:21 CET 2018
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29934
Change subject: Untangle CBFS microcode updates
......................................................................
Untangle CBFS microcode updates
Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e
Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
M Makefile.inc
M src/cpu/Kconfig
M src/cpu/Makefile.inc
M src/cpu/amd/family_10h-family_15h/Kconfig
M src/cpu/amd/family_10h-family_15h/Makefile.inc
M src/cpu/intel/fsp_model_406dx/Kconfig
M src/cpu/intel/microcode/Makefile.inc
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/fsp_baytrail/Kconfig
M src/soc/intel/fsp_broadwell_de/Kconfig
M src/soc/intel/icelake/Kconfig
12 files changed, 61 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29934/1
diff --git a/Makefile.inc b/Makefile.inc
index aaae7bc..e24c859 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1048,7 +1048,7 @@
$(FIT_OPTIONS)
endif
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y)
+ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
@printf " UPDATE-FIT\n"
$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
$(FIT_OPTIONS)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index a7cb99e..807a4ce 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -84,14 +84,27 @@
This is selected by a board or chipset to set the default for the
microcode source choice to a list of external microcode headers
+config POOR_MICROCODE_MAINTENANCE
+ bool
+ help
+ Selected by platforms that don't maintain microcode updates in the
+ blobs repo.
+
+config USE_CPU_MICROCODE_CBFS_BINS
+ bool
+ help
+ Selected to add binary microcode files (`cpu_microcode_bins` in the
+ makefiles) to CBFS.
+
choice
prompt "Include CPU microcode in CBFS" if ARCH_X86
default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
- default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
- default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
+ default CPU_MICROCODE_CBFS_NONE if POOR_MICROCODE_MAINTENANCE
+ depends on SUPPORT_CPU_UCODE_IN_CBFS
-config CPU_MICROCODE_CBFS_GENERATE
+config CPU_MICROCODE_CBFS_DEFAULT_BINS
bool "Generate from tree"
+ select USE_CPU_MICROCODE_CBFS_BINS
help
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
@@ -102,8 +115,27 @@
If unsure, select this option.
+config CPU_MICROCODE_CBFS_EXTERNAL_BINS
+ bool "Include external microcode binary"
+ select USE_CPU_MICROCODE_CBFS_BINS
+ depends on !CPU_MICROCODE_MULTIPLE_FILES
+ help
+ Select this option if you want to include external binary files
+ in the CPUs native format. They will be included as a separate
+ file in CBFS.
+
+ A word of caution: only select this option if you are sure the
+ microcode that you have is newer than the microcode shipping with
+ coreboot.
+
+ The microcode file may be removed from the ROM image at a later
+ time with cbfstool, if desired.
+
+ If unsure, and applicable, select "Generate from tree"
+
config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
bool "Include external microcode header files"
+ depends on !CPU_MICROCODE_MULTIPLE_FILES
help
Select this option if you want to include external c header files
containing the CPU microcode. This will be included as a separate
@@ -116,25 +148,17 @@
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
- If unsure, select "Generate from tree"
+ If unsure, and applicable, select "Generate from tree"
config CPU_MICROCODE_CBFS_NONE
bool "Do not include microcode updates"
help
Select this option if you do not want CPU microcode included in CBFS.
- Note that for some CPUs, the microcode is hard-coded into the source
- tree and is not loaded from CBFS. In this case, microcode will still
- be updated. There is a push to move all microcode to CBFS, but this
- change is not implemented for all CPUs.
-
- This option currently applies to:
- - Intel SandyBridge/IvyBridge
- - VIA Nano
Microcode may be added to the ROM image at a later time with cbfstool,
if desired.
- If unsure, select "Generate from tree"
+ If unsure, and applicable, select "Generate from tree"
The GOOD:
Microcode updates intend to solve issues that have been discovered
@@ -164,8 +188,6 @@
config CPU_MICROCODE_MULTIPLE_FILES
bool
- default n
- depends on CPU_MICROCODE_CBFS_GENERATE
help
Select this option to install separate microcode container files into
CBFS instead of using the traditional monolithic microcode file format.
@@ -179,7 +201,7 @@
config CPU_UCODE_BINARIES
string "Microcode binary path and filename"
- depends on CPU_MICROCODE_CBFS_GENERATE
+ depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS
default ""
help
Some platforms have microcode in the blobs directory, and these can
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 72fc29c..57241f6 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -17,7 +17,7 @@
################################################################################
ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin
+cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
endif
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
@@ -29,6 +29,11 @@
util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
+cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
+endif
+# otherwise `cpu_microcode_bins` should be filled by platform makefiles
+
# We just mash all microcode binaries together into one binary to rule them all.
# This approach assumes that the microcode binaries are properly padded, and
# their headers specify the correct size. This works fairly well on isolatied
@@ -37,21 +42,26 @@
# there is only one microcode binary (i.e. one container), then we don't have
# this issue, and this rule will continue to work.
$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
+ NO_MICROCODE_BINS=1; \
for bin in $(cpu_microcode_bins); do \
+ NO_MICROCODE_BINS=0; \
if [ ! -f "$$bin" ]; then \
echo "Microcode error: $$bin does not exist"; \
NO_MICROCODE_FILE=1; \
fi; \
done; \
if [ -n "$$NO_MICROCODE_FILE" ]; then \
- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)" ]; then \
+ if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
fi; \
false; \
fi
+ if [ "$$NO_MICROCODE_BINS" -eq 1 ]; then \
+ false; \
+ fi
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
@echo $(cpu_microcode_bins)
- cat /dev/null $+ > $@
+ cat $+ > $@
cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
cpu_microcode_blob.bin-type := microcode
diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
index 8e90247..5193d1d 100644
--- a/src/cpu/amd/family_10h-family_15h/Kconfig
+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
@@ -10,7 +10,7 @@
select UDELAY_LAPIC
select HAVE_MONOTONIC_TIMER
select SUPPORT_CPU_UCODE_IN_CBFS
- select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE
+ select CPU_MICROCODE_MULTIPLE_FILES
select ACPI_HUGE_LOWMEM_BACKUP
if CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 2ed76e1..7035323 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -15,11 +15,11 @@
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
# Microcode for Family 10h, 11h, 12h, and 14h
-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
+cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
microcode_amd.bin-type := microcode
# Microcode for Family 15h
-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
+cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
microcode_amd_fam15h.bin-type := microcode
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 4c79b23..1f73749 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -29,6 +29,7 @@
select SSE2
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
+ select POOR_MICROCODE_MAINTENANCE
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index b56e6a7..f589430 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -4,5 +4,3 @@
################################################################################
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
-
-cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 4a841be..66db8db 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -31,6 +31,7 @@
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select IOAPIC
select PCR_COMMON_IOSF_1_0
+ select POOR_MICROCODE_MAINTENANCE
select SMP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 9452b6d..a9a511e 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -46,6 +46,7 @@
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
+ select POOR_MICROCODE_MAINTENANCE
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 7d82f3f..a8d9fd4 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -41,6 +41,7 @@
select TSC_SYNC_MFENCE
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
+ select POOR_MICROCODE_MAINTENANCE
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SPI_CONSOLE_SUPPORT
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index fe0fa8d..88ba382 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -21,6 +21,7 @@
select IOAPIC
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
+ select POOR_MICROCODE_MAINTENANCE
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 727fccee..bd53c8b 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -33,6 +33,7 @@
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
+ select POOR_MICROCODE_MAINTENANCE
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
--
To view, visit https://review.coreboot.org/c/coreboot/+/29934
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e
Gerrit-Change-Number: 29934
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
Gerrit-MessageType: newchange
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