[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Load FSP teardown optionally

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29907


Change subject: soc/intel/cannonlake: Load FSP teardown optionally
......................................................................

soc/intel/cannonlake: Load FSP teardown optionally

Make build still pass in case of no FsptUpd.h available.

BUG=N/A
TEST=Delete FsptUpd.h and build pass wihtout FSP_CAR set.

Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/bootblock/bootblock.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29907/1

diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 4eeef59..b7d00cd 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -19,6 +19,8 @@
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/pch.h>
+
+#if IS_ENABLED(CONFIG_FSP_CAR)
 #include <FsptUpd.h>
 
 const FSPT_UPD temp_ram_init_params = {
@@ -37,6 +39,7 @@
 		.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
 	},
 };
+#endif
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {

-- 
To view, visit https://review.coreboot.org/c/coreboot/+/29907
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc
Gerrit-Change-Number: 29907
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-MessageType: newchange
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181129/692b47e6/attachment.html>