[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common: Rework acpi/cpu.asl
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Nov 28 12:50:00 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29891
Change subject: soc/intel/common: Rework acpi/cpu.asl
......................................................................
soc/intel/common: Rework acpi/cpu.asl
Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/soc/intel/apollolake/acpi/cpu.asl
M src/soc/intel/cannonlake/acpi/cpu.asl
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/icelake/acpi/cpu.asl
4 files changed, 51 insertions(+), 135 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29891/1
diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl
index a202ceb..8b2e080 100644
--- a/src/soc/intel/apollolake/acpi/cpu.asl
+++ b/src/soc/intel/apollolake/acpi/cpu.asl
@@ -13,106 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
Method (PPCN)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x80) // _PPC
- Notify (\_PR.CP01, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x80) // _PPC
- Notify (\_PR.CP03, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x80) // _PPC
- Notify (\_PR.CP05, 0x80) // _PPC
- Notify (\_PR.CP06, 0x80) // _PPC
- Notify (\_PR.CP07, 0x80) // _PPC
- }
+ \_PR.CNOT (0x81)
}
/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
Method (TNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x82) // _TPC
- Notify (\_PR.CP01, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x82) // _TPC
- Notify (\_PR.CP03, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x82) // _TPC
- Notify (\_PR.CP05, 0x82) // _TPC
- Notify (\_PR.CP06, 0x82) // _TPC
- Notify (\_PR.CP07, 0x82) // _TPC
- }
-}
-
-/* Return a package containing enabled processor entries */
-Method (PPKG)
-{
- If (LGreaterEqual (\PCNT, 8)) {
- Return (Package()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03,
- \_PR.CP04,
- \_PR.CP05,
- \_PR.CP06,
- \_PR.CP07
- })
- } ElseIf (LGreaterEqual (\PCNT, 4)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03
- })
- } ElseIf (LGreaterEqual (\PCNT, 2)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01
- })
- } Else {
- Return (Package ()
- {
- \_PR.CP00
- })
- }
-}
+ \_PR.CNOT (0x82)
+}
\ No newline at end of file
diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl
index 79314e6..7c074b8 100644
--- a/src/soc/intel/cannonlake/acpi/cpu.asl
+++ b/src/soc/intel/cannonlake/acpi/cpu.asl
@@ -13,31 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
+}
\ No newline at end of file
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 870e371..0b62a73 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -436,6 +436,21 @@
acpigen_pop_len();
}
}
+ /* PPKG is usually used for thermal management
+ of the first and only package. */
+ acpigen_write_processor_package("PPKG", 0, cores_per_package);
+
+ /* Add a method to notify processor nodes */
+ acpigen_write_method("\\_PR.CNOT", 1);
+ for (core_id = 0; core_id < cores_per_package; core_id++) {
+ char buffer[DEVICE_PATH_MAX];
+ snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c",
+ '0' + core_id / 10, '0' + core_id % 10);
+ acpigen_emit_byte(NOTIFY_OP);
+ acpigen_emit_namestring(buffer);
+ acpigen_emit_byte(ARG0_OP);
+ }
+ acpigen_pop_len();
}
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl
index be6e793..76d2201 100644
--- a/src/soc/intel/icelake/acpi/cpu.asl
+++ b/src/soc/intel/icelake/acpi/cpu.asl
@@ -13,31 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
+}
\ No newline at end of file
--
To view, visit https://review.coreboot.org/c/coreboot/+/29891
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Gerrit-Change-Number: 29891
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-MessageType: newchange
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181128/92028298/attachment-0001.html>
More information about the coreboot-gerrit
mailing list