[coreboot-gerrit] Change in ...coreboot[master]: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29882 )

Change subject: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
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Patch Set 2: Code-Review+2


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Gerrit-Change-Number: 29882
Gerrit-PatchSet: 2
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 28 Nov 2018 09:49:38 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
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