[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29866 )

Change subject: nb/intel/gm45: Correctly cache TSEG
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Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/29866/3/src/northbridge/intel/gm45/ram_calc.c 
File src/northbridge/intel/gm45/ram_calc.c:

https://review.coreboot.org/#/c/29866/3/src/northbridge/intel/gm45/ram_calc.c@87 
PS3, Line 87: uintptr_t smm_region_start(void)
Could be static now. Could also rename this to `northbridge_get_tseg_base`.
And remove the declaration in `gm45.h`.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Gerrit-Change-Number: 29866
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Tue, 27 Nov 2018 13:38:00 +0000
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