[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/29866

to look at the new patch set (#2).

Change subject: nb/intel/gm45: Correctly cache TSEG
......................................................................

nb/intel/gm45: Correctly cache TSEG

Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
2 files changed, 16 insertions(+), 19 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Gerrit-Change-Number: 29866
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-MessageType: newpatchset
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