[coreboot-gerrit] Change in coreboot[master]: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support

Sat Nov 17 11:39:07 CET 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29667 )

Change subject: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support
......................................................................

Patch Set 1:

(23 comments)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/boot.c
File src/arch/x86/boot.c:

https://review.coreboot.org/#/c/29667/1/src/arch/x86/boot.c@36
PS1, Line 36: 	printk(BIOS_DEBUG, "Jumping to %p\n", (void*)prog_entry(prog));
"(foo*)" should be "(foo *)"

https://review.coreboot.org/#/c/29667/1/src/arch/x86/include/arch/mmu.h
File src/arch/x86/include/arch/mmu.h:

https://review.coreboot.org/#/c/29667/1/src/arch/x86/include/arch/mmu.h@78
PS1, Line 78: #define L0_ADDR_MASK     (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT)
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/include/arch/mmu.h@79
PS1, Line 79: #define L1_ADDR_MASK     (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/include/arch/mmu.h@80
PS1, Line 80: #define L2_ADDR_MASK     (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/include/arch/mmu.h@81
PS1, Line 81: #define L3_ADDR_MASK     (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c
File src/arch/x86/mmu.c:

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@214
PS1, Line 214: 	if ((size >= L1_XLAT_SIZE) &&
suspect code indent for conditional statements (8, 24)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@274
PS1, Line 274: 		switch ((pte[index] & AVAIL_MASK) >> AVAIL_SHIFT) {
switch and case should be at the same indent

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@276
PS1, Line 276: 				printk(BIOS_DEBUG, "INVAL ");break;
space required after that ';' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@278
PS1, Line 278: 				printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break;
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@278
PS1, Line 278: 				printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break;
space required after that ';' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@280
PS1, Line 280: 				printk(BIOS_DEBUG, "PAGE %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)),
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@281
PS1, Line 281: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@281
PS1, Line 281: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
need consistent spacing around '-' (ctx:WxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@281
PS1, Line 281: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@281
PS1, Line 281: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
space required after that ';' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@284
PS1, Line 284: 			printk(BIOS_DEBUG, "BLOCK %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)),
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@285
PS1, Line 285: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@285
PS1, Line 285: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
need consistent spacing around '-' (ctx:WxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@285
PS1, Line 285: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@285
PS1, Line 285: 			(pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break;
space required after that ';' (ctx:VxV)

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@340
PS1, Line 340: 		next_free_table = cbmem_add(CBMEM_ID_TTB, CONFIG_TTB_SIZE_KB * 1024);
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/arch/x86/mmu.c@390
PS1, Line 390: 	#define MSR_EFER		0xc0000080 /* extended feature register */
line over 80 characters

https://review.coreboot.org/#/c/29667/1/src/mainboard/emulation/qemu-q35/romstage.c
File src/mainboard/emulation/qemu-q35/romstage.c:

https://review.coreboot.org/#/c/29667/1/src/mainboard/emulation/qemu-q35/romstage.c@43
PS1, Line 43: 		mmu_config_range(0x100000000ULL, (uint64_t)qemu_get_high_memory_size() * 1024ULL, PAT_WB);
line over 80 characters

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Gerrit-Change-Number: 29667
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Ronald G. Minnich <rminnich at gmail.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer at coreboot.org>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Sat, 17 Nov 2018 10:39:07 +0000
Gerrit-HasComments: Yes
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