[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add options for pcie ltr

Pratikkumar V Prajapati (Code Review) gerrit at coreboot.org
Thu Nov 15 06:47:30 CET 2018


Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/29642 )

Change subject: soc/intel/cannonlake: Add options for pcie ltr
......................................................................


Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/29642/1//COMMIT_MSG
Commit Message:

https://review.coreboot.org/#/c/29642/1//COMMIT_MSG@10
PS1, Line 10: mechansism 
mechanism



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Gerrit-Project: coreboot
Gerrit-Branch: master
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Gerrit-Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Gerrit-Change-Number: 29642
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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