[coreboot-gerrit] Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Wed Nov 14 17:55:14 CET 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29638
Change subject: SMBIOS: Remove duplicated smbios_memory_type enum
......................................................................
SMBIOS: Remove duplicated smbios_memory_type enum
Also, rename "clock_speed" to "memory_speed" as per
SMBIOS spec version 3.2.0
Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/arch/x86/smbios.c
M src/include/memory_info.h
M src/include/smbios.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/cyan/spd/spd.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/intel/nehalem/raminit.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
8 files changed, 18 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29638/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index c0545ce..babe61b 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -276,7 +276,7 @@
memset(t, 0, sizeof(struct smbios_type17));
t->memory_type = dimm->ddr_type;
- t->clock_speed = dimm->ddr_frequency;
+ t->memory_speed = dimm->ddr_frequency;
t->speed = dimm->ddr_frequency;
t->type = SMBIOS_MEMORY_DEVICE;
if (dimm->dimm_size < 0x7fff) {
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 5976e31..93c7b6b 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -36,7 +36,7 @@
/*
* SMBIOS (not SPD) device type.
*
- * See the smbios.h smbios_memory_device_type enum.
+ * See the smbios.h smbios_memory_type enum.
*/
uint16_t ddr_type;
uint16_t ddr_frequency;
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 574b924..91777e3 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -97,36 +97,6 @@
} smbios_memory_bus_width;
typedef enum {
- MEMORY_DEVICE_OTHER = 0x01,
- MEMORY_DEVICE_UNKNOWN = 0x02,
- MEMORY_DEVICE_DRAM = 0x03,
- MEMORY_DEVICE_EDRAM = 0x04,
- MEMORY_DEVICE_VRAM = 0x05,
- MEMORY_DEVICE_SRAM = 0x06,
- MEMORY_DEVICE_RAM = 0x07,
- MEMORY_DEVICE_ROM = 0x08,
- MEMORY_DEVICE_FLASH = 0x09,
- MEMORY_DEVICE_EEPROM = 0x0A,
- MEMORY_DEVICE_FEPROM = 0x0B,
- MEMORY_DEVICE_EPROM = 0x0C,
- MEMORY_DEVICE_CDRAM = 0x0D,
- MEMORY_DEVICE_3DRAM = 0x0E,
- MEMORY_DEVICE_SDRAM = 0x0F,
- MEMORY_DEVICE_SGRAM = 0x10,
- MEMORY_DEVICE_RDRAM = 0x11,
- MEMORY_DEVICE_DDR = 0x12,
- MEMORY_DEVICE_DDR2 = 0x13,
- MEMORY_DEVICE_DDR2_FB_DIMM = 0x14,
- MEMORY_DEVICE_DDR3 = 0x18,
- MEMORY_DEVICE_DBD2 = 0x19,
- MEMORY_DEVICE_DDR4 = 0x1A,
- MEMORY_DEVICE_LPDDR = 0x1B,
- MEMORY_DEVICE_LPDDR2 = 0x1C,
- MEMORY_DEVICE_LPDDR3 = 0x1D,
- MEMORY_DEVICE_LPDDR4 = 0x1E,
-} smbios_memory_device_type;
-
-typedef enum {
MEMORY_FORMFACTOR_OTHER = 0x01,
MEMORY_FORMFACTOR_UNKNOWN = 0x02,
MEMORY_FORMFACTOR_SIMM = 0x03,
@@ -167,6 +137,12 @@
MEMORY_TYPE_DDR2_FBDIMM = 0x14,
MEMORY_TYPE_DDR3 = 0x18,
MEMORY_TYPE_FBD2 = 0x19,
+ MEMORY_TYPE_DDR4 = 0x1a,
+ MEMORY_TYPE_LPDDR = 0x1b,
+ MEMORY_TYPE_LPDDR2 = 0x1c,
+ MEMORY_TYPE_LPDDR3 = 0x1d,
+ MEMORY_TYPE_LPDDR4 = 0x1e,
+ MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f,
} smbios_memory_type;
typedef enum {
@@ -474,7 +450,7 @@
u8 part_number;
u8 attributes;
u32 extended_size;
- u16 clock_speed;
+ u16 memory_speed;
u16 minimum_voltage;
u16 maximum_voltage;
u16 configured_voltage;
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 9d9225c..3eff307 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -202,7 +202,7 @@
t->memory_type = 0x12; /* DDR */
t->type_detail = 0x80; /* Synchronous */
t->speed = 200;
- t->clock_speed = 200;
+ t->memory_speed = 200;
t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
len = t->length + smbios_string_table_len(t->eos);
*current += len;
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index 7682677..b7b0c30 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -138,9 +138,9 @@
/* Parse the SPD data to determine the DIMM information */
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
- dimm->ddr_type = MEMORY_DEVICE_DDR3;
+ dimm->ddr_type = MEMORY_TYPE_DDR3;
} else {
- dimm->ddr_type = MEMORY_DEVICE_LPDDR3;
+ dimm->ddr_type = MEMORY_TYPE_LPDDR3;
}
dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */
dimm->mod_type = spd[3] & 0xf;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 4da5228..912d0a0 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1239,7 +1239,7 @@
else
t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED;
t->speed = max_speed;
- t->clock_speed = speed;
+ t->memory_speed = speed;
smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t);
t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]);
if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) {
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index ee5a60b..6ef7ed7 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -185,7 +185,7 @@
#define gav(x) gav_real (__LINE__, (x))
struct raminfo {
- u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
+ u16 clock_speed_index; /* memory_speed (REAL, not DDR) / 133.(3) - 3 */
u16 fsb_frequency; /* in 1.(1)/2 MHz. */
u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */
u8 density[2][2]; /* [CHANNEL][SLOT] */
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 0945780..eed9d8b 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -103,16 +103,16 @@
switch(memory_info_hob->MemoryType) {
case MRC_DDR_TYPE_DDR4:
- ddr_type = MEMORY_DEVICE_DDR4;
+ ddr_type = MEMORY_TYPE_DDR4;
break;
case MRC_DDR_TYPE_DDR3:
- ddr_type = MEMORY_DEVICE_DDR3;
+ ddr_type = MEMORY_TYPE_DDR3;
break;
case MRC_DDR_TYPE_LPDDR3:
- ddr_type = MEMORY_DEVICE_LPDDR3;
+ ddr_type = MEMORY_TYPE_LPDDR3;
break;
default:
- ddr_type = MEMORY_DEVICE_UNKNOWN;
+ ddr_type = MEMORY_TYPE_UNKNOWN;
break;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e
Gerrit-Change-Number: 29638
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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