[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Remove SmbusEnable

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29552 )

Change subject: soc/intel/cannonlake: Remove SmbusEnable
......................................................................

soc/intel/cannonlake: Remove SmbusEnable

Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.

Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie at google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 5 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2deb35f..015133e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -166,9 +166,6 @@
 	 * clksrc. */
 	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
 
-	/* SMBus */
-	uint8_t SmbusEnable;
-
 	/* eMMC and SD */
 	uint8_t ScsEmmcHs400Enabled;
 	/* Need to update DLL setting to get Emmc running at HS400 speed */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 8506214..8f6fa2f 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -66,6 +66,7 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS);
 	assert(dev != NULL);
 	const config_t *config = dev->chip_info;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -73,7 +74,10 @@
 	soc_memory_init_params(m_cfg, config);
 
 	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
+	if (!smbus)
+		m_cfg->SmbusEnable = 0;
+	else
+		m_cfg->SmbusEnable = smbus->enabled;
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent = config->DebugConsent;
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Gerrit-Change-Number: 29552
Gerrit-PatchSet: 2
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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