[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29530 )

Change subject: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
......................................................................

siemens/mc_apl3: Set Full Reset Bit into Reset Control Register

This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 and then the reset button
is pressed the PCH will drive SLP_S3 active (low).

Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
Reviewed-on: https://review.coreboot.org/29530
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved



diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index f41fe73..3a87a4f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -14,6 +14,7 @@
  */
 
 #include <bootstate.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -62,6 +63,13 @@
 		cmd |= PCI_COMMAND_MASTER;
 		pci_write_config16(dev, PCI_COMMAND, cmd);
 	}
+
+	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
+	 * When Bit 3 is set to 1 and then the reset button is pressed the PCH
+	 * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard
+	 * to generate the right reset timing.
+	 */
+	outb(FULL_RST, RST_CNT);
 }
 
 static void wait_for_legacy_dev(void *unused)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Gerrit-Change-Number: 29530
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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