[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges

[Mario Scheithauer (Code Review)]

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/29549 )

Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
......................................................................


Patch Set 4:

(1 comment)

https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
File src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c:

https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c@73
PS4, Line 73: dev->bus->dev->device
> So do you need dev->bus->dev->device or dev->device which is used in the upper case?
In the above case, I set the parent device before the if instruction to dev object (line 64). Because of the 80 character rule, the if instruction is then better readable.
In the second case, I don't take the intermediate step.



-- 
To view, visit https://review.coreboot.org/29549
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Gerrit-Change-Number: 29549
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 08 Nov 2018 15:40:50 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181108/ee4353f0/attachment.html>