[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges

[Mario Scheithauer (Code Review)]

Hello Werner Zeh, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/29549

to look at the new patch set (#4).

Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
......................................................................

siemens/mc_apl3: Disable PCI clock outputs on XIO bridges

On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.

Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 14 insertions(+), 5 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Gerrit-Change-Number: 29549
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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