[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequ...

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/29473

to review the following change.


Change subject: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequences
......................................................................

mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequences

add 20ms adjust timing for edp panel in devicetree.

BUG=b:118011567
TEST=verify panel sequences by ODM

Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690
Signed-off-by: Chris Wang <chris.wang at amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/variants/liara/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29473/1

diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
index 343fbeb..eef984a 100644
--- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
@@ -20,6 +20,8 @@
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
 	register "uma_size" = "32 * MiB"
+	register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
+	register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms
 
 	# Enable I2C0 for audio, USB3 hub at 400kHz
 	register "i2c[0]" = "{

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690
Gerrit-Change-Number: 29473
Gerrit-PatchSet: 1
Gerrit-Owner: chris wang <Chris.Wang at amd.com>
Gerrit-Reviewer: Chris Wang <chris.wang at amd.corp-partner.google.com>
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