[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 6:

(1 comment)

https://review.coreboot.org/#/c/25442/6/src/soc/intel/denverton_ns/lpc.c
File src/soc/intel/denverton_ns/lpc.c:

https://review.coreboot.org/#/c/25442/6/src/soc/intel/denverton_ns/lpc.c@419
PS6, Line 419: 	if(!relax_security)
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 6
Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju at vdg.name>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Jay Talbott <JayTalbott at sysproconsulting.com>
Gerrit-CC: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Comment-Date: Fri, 02 Nov 2018 14:58:05 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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