[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29417 )

Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
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Patch Set 1:

> Patch Set 1:
> 
> Please use runtime detection and ssdt code to achieve the same functionality.

The standard Intel FSP disables both SPI1 and PWM. All system using this FSP will not have the SPI1 and PWM enabled. Adding runtime detection will take boot time, where the result will be constant on these system. 

I dont know if Google Cyan use standard FSP binary. If so I suggest removing the SPI1 and PWM ASL code. 
For Google Cyan the SP1 and PWM ASL code can be added to mainboard directory when required.

I suggest to move this code to Google Cyan?


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606
Gerrit-Change-Number: 29417
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Patrick Rudolph <siro at das-labor.org>
Gerrit-Comment-Date: Fri, 02 Nov 2018 12:59:08 +0000
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