[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add FSP CAR support for kabylake

[PraveenX Hodagatta Pranesh (Code Review)]

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29433


Change subject: soc/intel/skylake: Add FSP CAR support for kabylake
......................................................................

soc/intel/skylake: Add FSP CAR support for kabylake

Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.

This patch add FSP CAR support for kabylake by programming tempraminit
parameters in bootblock.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.

BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
     for successful FSP CAR setup.

Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/bootblock.c
2 files changed, 19 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29433/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 1449d3d..2db8217 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -77,6 +77,7 @@
 	select TSC_MONOTONIC_TIMER
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
+	select FSP_T_XIP if FSP_CAR
 
 config CPU_INTEL_NUM_FIT_ENTRIES
 	int
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index a2bcaaf..309cf35 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -18,6 +18,24 @@
 #include <intelblocks/gspi.h>
 #include <intelblocks/uart.h>
 #include <soc/bootblock.h>
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+	.FspUpdHeader = {
+		.Signature = 0x545F4450554C424B,	/* 'KBLUPD_T' */
+		.Revision = 1,
+		.Reserved = {0},
+	},
+	.FsptCoreUpd = {
+		.MicrocodeRegionBase =
+			(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
+		.MicrocodeRegionSize =
+			(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+		.CodeRegionBase =
+			(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
+		.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
+	},
+};
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Gerrit-Change-Number: 29433
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
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