[coreboot-gerrit] Change in coreboot[master]: intel/common/pch/i2c: Move i2c file to common PCH
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu May 31 12:10:20 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26729
Change subject: intel/common/pch/i2c: Move i2c file to common PCH
......................................................................
intel/common/pch/i2c: Move i2c file to common PCH
i2c.c file is common across soc which uses common PCH base code.
Move i2c related files from cannonlake and skylake to PCH base code.
BUG=none
BRANCH=none
TEST= Check if code compiles with the patch and boot with SKL/CNL boards
Change-Id: I333ca3f3e96505993c81fd3113c68d1f92b8f1b8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/common/pch/Kconfig
A src/soc/intel/common/pch/i2c/Kconfig
A src/soc/intel/common/pch/i2c/Makefile.inc
R src/soc/intel/common/pch/i2c/i2c.c
M src/soc/intel/skylake/Makefile.inc
D src/soc/intel/skylake/i2c.c
7 files changed, 10 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/26729/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 4cce5c3..f070723 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -14,7 +14,6 @@
bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
-bootblock-y += i2c.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
@@ -23,7 +22,6 @@
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
romstage-y += gpio.c
-romstage-y += i2c.c
romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c
@@ -38,7 +36,6 @@
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += gpio.c
-ramstage-y += i2c.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += memmap.c
@@ -64,7 +61,6 @@
postcar-y += pmutil.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
-verstage-y += i2c.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 9014647..ff58524 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -45,4 +45,5 @@
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_PCH_LOCKDOWN
select SOC_INTEL_COMMON_PCH_GSPI
+ select SOC_INTEL_COMMON_PCH_I2C
endif
diff --git a/src/soc/intel/common/pch/i2c/Kconfig b/src/soc/intel/common/pch/i2c/Kconfig
new file mode 100644
index 0000000..1809cb6
--- /dev/null
+++ b/src/soc/intel/common/pch/i2c/Kconfig
@@ -0,0 +1,5 @@
+config SOC_INTEL_COMMON_PCH_I2C
+ bool
+ default n
+ help
+ This option allows to have i2c configuration for supported PCH.
diff --git a/src/soc/intel/common/pch/i2c/Makefile.inc b/src/soc/intel/common/pch/i2c/Makefile.inc
new file mode 100644
index 0000000..04328b7
--- /dev/null
+++ b/src/soc/intel/common/pch/i2c/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/common/pch/i2c/i2c.c
similarity index 100%
rename from src/soc/intel/cannonlake/i2c.c
rename to src/soc/intel/common/pch/i2c/i2c.c
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 8f673c3..03b293a 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -11,7 +11,6 @@
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
-bootblock-y += i2c.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
@@ -22,12 +21,10 @@
bootblock-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += pmutil.c
-verstage-y += i2c.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c
-romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += me.c
romstage-y += pei_data.c
@@ -44,7 +41,6 @@
ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += gpio.c
-ramstage-y += i2c.c
ramstage-y += graphics.c
ramstage-y += irq.c
ramstage-y += lockdown.c
diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c
deleted file mode 100644
index 9fd9bf3..0000000
--- a/src/soc/intel/skylake/i2c.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- * Copyright (C) 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <intelblocks/chip.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
- switch (devfn) {
- case PCH_DEVFN_I2C0:
- return 0;
- case PCH_DEVFN_I2C1:
- return 1;
- case PCH_DEVFN_I2C2:
- return 2;
- case PCH_DEVFN_I2C3:
- return 3;
- case PCH_DEVFN_I2C4:
- return 4;
- case PCH_DEVFN_I2C5:
- return 5;
- }
- return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
- switch (bus) {
- case 0:
- return PCH_DEVFN_I2C0;
- case 1:
- return PCH_DEVFN_I2C1;
- case 2:
- return PCH_DEVFN_I2C2;
- case 3:
- return PCH_DEVFN_I2C3;
- case 4:
- return PCH_DEVFN_I2C4;
- case 5:
- return PCH_DEVFN_I2C5;
- }
- return -1;
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I333ca3f3e96505993c81fd3113c68d1f92b8f1b8
Gerrit-Change-Number: 26729
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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