[coreboot-gerrit] Change in coreboot[master]: google/kukui: Add new board
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Thu May 31 03:27:47 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/26722
Change subject: google/kukui: Add new board
......................................................................
google/kukui: Add new board
BUG=none
BRANCH=none
TEST=timer and uart work fine
Change-Id: I08644892d34925574f791b000b0035d5afad7022
Signed-off-by: Tristan Shieh <tristan.shieh at mediatek.com>
---
A src/mainboard/google/kukui/Kconfig
A src/mainboard/google/kukui/Kconfig.name
A src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/board_info.txt
A src/mainboard/google/kukui/chromeos.c
A src/mainboard/google/kukui/chromeos.fmd
A src/mainboard/google/kukui/devicetree.cb
A src/mainboard/google/kukui/memlayout.ld
A src/mainboard/google/kukui/romstage.c
9 files changed, 165 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/26722/1
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
new file mode 100644
index 0000000..91e7aa9
--- /dev/null
+++ b/src/mainboard/google/kukui/Kconfig
@@ -0,0 +1,22 @@
+if BOARD_GOOGLE_KUKUI
+
+config BOARD_SPECIFIC_OPTIONS #dummy
+ def_bool y
+ select SOC_MEDIATEK_MT8183
+ select BOARD_ROMSIZE_KB_4096
+ select MAINBOARD_HAS_CHROMEOS
+ select CHROMEOS
+ select COMMON_CBFS_SPI_WRAPPER
+ select SPI_FLASH
+ select FATAL_ASSERTS
+ select VBOOT_MOCK_SECDATA
+
+config MAINBOARD_DIR
+ string
+ default google/kukui
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "KUKUI"
+
+endif
diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name
new file mode 100644
index 0000000..c568891
--- /dev/null
+++ b/src/mainboard/google/kukui/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_KUKUI
+ bool "KUKUI"
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
new file mode 100644
index 0000000..44a60b5
--- /dev/null
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -0,0 +1,11 @@
+bootblock-y += memlayout.ld
+
+verstage-y += chromeos.c
+verstage-y += memlayout.ld
+
+romstage-y += chromeos.c
+romstage-y += memlayout.ld
+romstage-y += romstage.c
+
+ramstage-y += chromeos.c
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/kukui/board_info.txt b/src/mainboard/google/kukui/board_info.txt
new file mode 100644
index 0000000..c3688c1
--- /dev/null
+++ b/src/mainboard/google/kukui/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Kukui MediaTek MT8183 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c
new file mode 100644
index 0000000..7f9946a
--- /dev/null
+++ b/src/mainboard/google/kukui/chromeos.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+}
+
+int get_recovery_mode_switch(void)
+{
+ return 0;
+}
+
+int get_write_protect_state(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd
new file mode 100644
index 0000000..9c618e3
--- /dev/null
+++ b/src/mainboard/google/kukui/chromeos.fmd
@@ -0,0 +1,29 @@
+FLASH at 0x0 0x400000 {
+ WP_RO at 0x0 0x200000 {
+ RO_SECTION at 0x0 0x1f0000 {
+ BOOTBLOCK at 0 128K
+ COREBOOT(CBFS)@0x20000 0xe0000
+ FMAP at 0x100000 0x1000
+ GBB at 0x101000 0xeef00
+ RO_FRID at 0x1eff00 0x100
+ }
+ RO_VPD at 0x1f0000 0x10000
+ }
+ RW_SECTION_A at 0x200000 0x78000 {
+ VBLOCK_A at 0x0 0x2000
+ FW_MAIN_A(CBFS)@0x2000 0x75f00
+ RW_FWID_A at 0x77f00 0x100
+ }
+ RW_SHARED at 0x278000 0x2000 {
+ SHARED_DATA at 0x0 0x2000
+ }
+ RW_NVRAM at 0x27a000 0x2000
+ RW_ELOG at 0x27c000 0x4000
+ RW_SECTION_B at 0x280000 0x78000 {
+ VBLOCK_B at 0x0 0x2000
+ FW_MAIN_B(CBFS)@0x2000 0x75f00
+ RW_FWID_B at 0x77f00 0x100
+ }
+ RW_VPD at 0x2f8000 0x8000
+ RW_LEGACY(CBFS)@0x300000 0x100000
+}
diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb
new file mode 100644
index 0000000..e2f2be3
--- /dev/null
+++ b/src/mainboard/google/kukui/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 MediaTek Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/mediatek/mt8183
+ device cpu_cluster 0 on
+ device cpu 0 on end
+ end
+end
diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld
new file mode 100644
index 0000000..2c33306
--- /dev/null
+++ b/src/mainboard/google/kukui/memlayout.ld
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
new file mode 100644
index 0000000..76a587d
--- /dev/null
+++ b/src/mainboard/google/kukui/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <timestamp.h>
+
+void main(void)
+{
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ /* init uart baudrate when pll on */
+ console_init();
+ exception_init();
+
+ run_ramstage();
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I08644892d34925574f791b000b0035d5afad7022
Gerrit-Change-Number: 26722
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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