[coreboot-gerrit] Change in coreboot[master]: src/northbridge: Remove whitespace before tab

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26603 )

Change subject: src/northbridge: Remove whitespace before tab
......................................................................


Patch Set 8:

(10 comments)

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/agesa/family14/chip.h
File src/northbridge/amd/agesa/family14/chip.h:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/agesa/family14/chip.h@30
PS8, Line 30: 	 *	{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdht/h3gtopo.h
File src/northbridge/amd/amdht/h3gtopo.h:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdht/h3gtopo.h@259
PS8, Line 259: 	0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF	// Node6
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdk8/raminit.c
File src/northbridge/amd/amdk8/raminit.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdk8/raminit.c@1310
PS8, Line 1310: 	uint8_t	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct/mct_d.c
File src/northbridge/amd/amdmct/mct/mct_d.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct/mct_d.c@3756
PS8, Line 3756: 	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct/mctdqs_d.c
File src/northbridge/amd/amdmct/mct/mctdqs_d.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct/mctdqs_d.c@464
PS8, Line 464: 		BanksPresent = 1;	/* flag for at least one bank is present */
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c@7912
PS8, Line 7912: 	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@118
PS8, Line 118: 	OB_ChipKill = mctGet_NVbits(NV_ChipKill);		/* ECC Chip-kill mode */
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@123
PS8, Line 123: 		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */	/* Need not adjust */
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@699
PS8, Line 699: 			//	wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
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https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/lx/northbridgeinit.c
File src/northbridge/amd/lx/northbridgeinit.c:

https://review.coreboot.org/#/c/26603/8/src/northbridge/amd/lx/northbridgeinit.c@597
PS8, Line 597:  *  SYSRC(7:0) = 00h		 ; writeback, can set to 08h to make writethrough
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935
Gerrit-Change-Number: 26603
Gerrit-PatchSet: 8
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 30 May 2018 07:17:26 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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