[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8183: Add a stub implementation of the MT8183 SOC

Tristan Hsieh (Code Review) gerrit at coreboot.org
Tue May 29 06:41:52 CEST 2018 

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/26659


Change subject: mediatek/mt8183: Add a stub implementation of the MT8183 SOC
......................................................................

mediatek/mt8183: Add a stub implementation of the MT8183 SOC

Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

BUG=none
BRANCH=none
TEST=timer and uart work fine

Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh at mediatek.com>
---
A src/mainboard/google/kukui/Kconfig
A src/mainboard/google/kukui/Kconfig.name
A src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/board_info.txt
A src/mainboard/google/kukui/chromeos.c
A src/mainboard/google/kukui/chromeos.fmd
A src/mainboard/google/kukui/devicetree.cb
A src/mainboard/google/kukui/memlayout.ld
A src/mainboard/google/kukui/romstage.c
A src/soc/mediatek/mt8183/Kconfig
A src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/cbmem.c
A src/soc/mediatek/mt8183/flash_controller.c
A src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/flash_controller.h
A src/soc/mediatek/mt8183/include/soc/memlayout.ld
A src/soc/mediatek/mt8183/spi.c
M util/mtkheader/gen-bl-img.py
18 files changed, 450 insertions(+), 16 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26659/1

diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
new file mode 100644
index 0000000..79679ad
--- /dev/null
+++ b/src/mainboard/google/kukui/Kconfig
@@ -0,0 +1,20 @@
+if BOARD_GOOGLE_KUKUI
+
+config BOARD_SPECIFIC_OPTIONS #dummy
+	def_bool y
+	select SOC_MEDIATEK_MT8183
+	select BOARD_ROMSIZE_KB_4096
+	select MAINBOARD_HAS_CHROMEOS
+	select COMMON_CBFS_SPI_WRAPPER
+	select SPI_FLASH
+	select FATAL_ASSERTS
+
+config MAINBOARD_DIR
+	string
+	default google/kukui
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "KUKUI"
+
+endif
diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name
new file mode 100644
index 0000000..c568891
--- /dev/null
+++ b/src/mainboard/google/kukui/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_KUKUI
+	bool "KUKUI"
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
new file mode 100644
index 0000000..44a60b5
--- /dev/null
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -0,0 +1,11 @@
+bootblock-y += memlayout.ld
+
+verstage-y += chromeos.c
+verstage-y += memlayout.ld
+
+romstage-y += chromeos.c
+romstage-y += memlayout.ld
+romstage-y += romstage.c
+
+ramstage-y += chromeos.c
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/kukui/board_info.txt b/src/mainboard/google/kukui/board_info.txt
new file mode 100644
index 0000000..c3688c1
--- /dev/null
+++ b/src/mainboard/google/kukui/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Kukui MediaTek MT8183 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c
new file mode 100644
index 0000000..7f9946a
--- /dev/null
+++ b/src/mainboard/google/kukui/chromeos.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd
new file mode 100644
index 0000000..9c618e3
--- /dev/null
+++ b/src/mainboard/google/kukui/chromeos.fmd
@@ -0,0 +1,29 @@
+FLASH at 0x0 0x400000 {
+	WP_RO at 0x0 0x200000 {
+		RO_SECTION at 0x0 0x1f0000 {
+			BOOTBLOCK at 0 128K
+			COREBOOT(CBFS)@0x20000 0xe0000
+			FMAP at 0x100000 0x1000
+			GBB at 0x101000 0xeef00
+			RO_FRID at 0x1eff00 0x100
+		}
+		RO_VPD at 0x1f0000 0x10000
+	}
+	RW_SECTION_A at 0x200000 0x78000 {
+		VBLOCK_A at 0x0 0x2000
+		FW_MAIN_A(CBFS)@0x2000 0x75f00
+		RW_FWID_A at 0x77f00 0x100
+	}
+	RW_SHARED at 0x278000 0x2000 {
+		SHARED_DATA at 0x0 0x2000
+	}
+	RW_NVRAM at 0x27a000 0x2000
+	RW_ELOG at 0x27c000 0x4000
+	RW_SECTION_B at 0x280000 0x78000 {
+		VBLOCK_B at 0x0 0x2000
+		FW_MAIN_B(CBFS)@0x2000 0x75f00
+		RW_FWID_B at 0x77f00 0x100
+	}
+	RW_VPD at 0x2f8000 0x8000
+	RW_LEGACY(CBFS)@0x300000 0x100000
+}
diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb
new file mode 100644
index 0000000..e2f2be3
--- /dev/null
+++ b/src/mainboard/google/kukui/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 MediaTek Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/mediatek/mt8183
+	device cpu_cluster 0 on
+		device cpu 0 on end
+	end
+end
diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld
new file mode 100644
index 0000000..2c33306
--- /dev/null
+++ b/src/mainboard/google/kukui/memlayout.ld
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
new file mode 100644
index 0000000..76a587d
--- /dev/null
+++ b/src/mainboard/google/kukui/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <timestamp.h>
+
+void main(void)
+{
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	/* init uart baudrate when pll on */
+	console_init();
+	exception_init();
+
+	run_ramstage();
+}
diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig
new file mode 100644
index 0000000..040e692
--- /dev/null
+++ b/src/soc/mediatek/mt8183/Kconfig
@@ -0,0 +1,21 @@
+config SOC_MEDIATEK_MT8183
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select ARM64_USE_ARM_TRUSTED_FIRMWARE
+	select BOOTBLOCK_CONSOLE
+	select GENERIC_UDELAY
+	select HAVE_UART_SPECIAL
+	select HAVE_MONOTONIC_TIMER
+
+if SOC_MEDIATEK_MT8183
+
+config VBOOT
+	select VBOOT_OPROM_MATTERS
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_SEPARATE_VERSTAGE
+
+endif
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
new file mode 100644
index 0000000..2ffec67
--- /dev/null
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -0,0 +1,32 @@
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
+
+bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
+bootblock-y += spi.c
+bootblock-y += ../common/timer.c
+ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
+bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+endif
+
+verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+verstage-y += spi.c
+verstage-y += ../common/timer.c
+verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+
+romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+romstage-y += spi.c
+romstage-y += ../common/timer.c
+romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+
+ramstage-y += cbmem.c
+ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+ramstage-y += spi.c
+ramstage-y += ../common/timer.c
+ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	./util/mtkheader/gen-bl-img.py mt8183 emmc $< $@
+
+endif
diff --git a/src/soc/mediatek/mt8183/cbmem.c b/src/soc/mediatek/mt8183/cbmem.c
new file mode 100644
index 0000000..1963578
--- /dev/null
+++ b/src/soc/mediatek/mt8183/cbmem.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	return (void *)((uintptr_t)4 * GiB);
+}
diff --git a/src/soc/mediatek/mt8183/flash_controller.c b/src/soc/mediatek/mt8183/flash_controller.c
new file mode 100644
index 0000000..2855493
--- /dev/null
+++ b/src/soc/mediatek/mt8183/flash_controller.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* this is a spi driver which adapt emmc to fake spi flash */
+
+#include <soc/flash_controller.h>
+#include <spi_flash.h>
+
+static void init_io(void)
+{
+}
+
+static int emmc_adapter_read(const struct spi_flash *flash, u32 addr,
+		size_t len, void *buf)
+{
+	return 0;
+}
+
+static int emmc_adapter_write(const struct spi_flash *flash, u32 addr,
+		size_t len, const void *buf)
+{
+	return 0;
+}
+
+static int emmc_adapter_erase(const struct spi_flash *flash, u32 offset,
+		size_t len)
+{
+	return 0;
+}
+
+const struct spi_flash_ops spi_emmc_flash_ops = {
+	.read = emmc_adapter_read,
+	.write = emmc_adapter_write,
+	.erase = emmc_adapter_erase,
+};
+
+int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash)
+{
+	init_io();
+
+	flash->name = "spi emmc flash controller";
+	flash->sector_size = 0x800;
+	flash->size = CONFIG_ROM_SIZE;
+
+	flash->ops = &spi_emmc_flash_ops;
+	return 0;
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
new file mode 100644
index 0000000..ad272b6
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#pragma once
+
+enum {
+	IO_PHYS		= 0x10000000,
+	DDR_BASE	= 0x40000000
+};
+
+enum {
+	GPT_BASE	= IO_PHYS + 0x00008000,
+	UART0_BASE	= IO_PHYS + 0x01002000,
+};
diff --git a/src/soc/mediatek/mt8183/include/soc/flash_controller.h b/src/soc/mediatek/mt8183/include/soc/flash_controller.h
new file mode 100644
index 0000000..222b7a6
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/flash_controller.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#pragma once
+
+#include <spi-generic.h>
+
+int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash);
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
new file mode 100644
index 0000000..33742bfd
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
+ * It will be returned before starting the ramstage.
+ * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
+ */
+#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
+#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
+
+#define DRAM_DMA(addr, size) \
+	REGION(dram_dma, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
+SECTIONS
+{
+	SRAM_START(0x00100000)
+	VBOOT2_WORK(0x00100000, 12K)
+	PRERAM_CBMEM_CONSOLE(0x00103000, 16K)
+	WATCHDOG_TOMBSTONE(0x00107000, 4)
+	PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
+	TIMESTAMP(0x0010B000, 4K)
+	STACK(0x0010C000, 16K)
+	TTB(0x00110000, 28K)
+	DMA_COHERENT(0x00117000, 4K)
+	SRAM_END(0x00120000)
+
+	SRAM_L2C_START(0x00200000)
+	BOOTBLOCK(0x00201000, 85K)
+	VERSTAGE(0x00217000, 114K)
+	ROMSTAGE(0x00233800, 92K)
+	SRAM_L2C_END(0x00280000)
+
+	DRAM_START(0x40000000)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 1M)
+	RAMSTAGE(0x40200000, 256K)
+}
diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c
new file mode 100644
index 0000000..78821d1
--- /dev/null
+++ b/src/soc/mediatek/mt8183/spi.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/flash_controller.h>
+#include <spi-generic.h>
+
+static const struct spi_ctrlr spi_flash_ctrlr = {
+	.max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_flash_ctrlr,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/util/mtkheader/gen-bl-img.py b/util/mtkheader/gen-bl-img.py
index 361912f..3f708c6 100755
--- a/util/mtkheader/gen-bl-img.py
+++ b/util/mtkheader/gen-bl-img.py
@@ -35,20 +35,26 @@
 def align(data, size, pattern = '\0'):
 	return padding(data, (len(data) + (size - 1)) & ~(size - 1), pattern)
 
-gfh_infos = {
-	'mt8173': struct.pack("44I",
-	0x014d4d4d, 0x00000038, 0x454c4946, 0x464e495f,
-	0x0000004f, 0x00000001, 0x01050001, 0x000C0f50,
-	0xffffffff, 0x00020000, 0x000000a8, 0x00000020,
-	0x000000B0, 0x00000001, 0x014d4d4d, 0x0001000c,
-	0x00000001, 0x034d4d4d, 0x00070064, 0x00001182,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00006400, 0x00001388,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    )}
+def gen_gfh_info(chip):
+	entries = {
+		'mt8173': 0x000C1000,
+		'mt8183': 0x00201000
+	}
+
+	gfh = struct.pack("44I",
+		0x014d4d4d, 0x00000038, 0x454c4946, 0x464e495f,
+		0x0000004f, 0x00000001, 0x01050001, entries[chip] - 0xb0,
+		0xffffffff, 0x00020000, 0x000000a8, 0x00000020,
+		0x000000B0, 0x00000001, 0x014d4d4d, 0x0001000c,
+		0x00000001, 0x034d4d4d, 0x00070064, 0x00001182,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00006400, 0x00001388,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000)
+
+	return gfh
 
 def gen_emmc_header(data):
 	header = (padding(struct.pack("<12sII", "EMMC_BOOT", 1, 512), 512, '\xff') +
@@ -70,7 +76,7 @@
 }
 
 def gen_preloader(chip_ver, flash_type, data):
-	gfh_info = gfh_infos[chip_ver]
+	gfh_info = gen_gfh_info(chip_ver)
 	gfh_info = gfh_info[0:32] + struct.pack("1I", len(data)+len(gfh_info)+32) + gfh_info[36:len(gfh_info)]
 
 	gfh_hash = hashlib.sha256(gfh_info + data).digest()
@@ -83,7 +89,7 @@
 	if len(argv) != 5:
 		print "Usage: %s <chip> <flash_type> <input_file> <output_file>" % argv[0]
 		print "\t flash_type: emmc/sf"
-		print "\t chip      : mt8173"
+		print "\t chip      : mt8173/mt8183"
 
 		exit(1)
 	write(argv[4], gen_preloader(argv[1], argv[2], read(argv[3])))

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Gerrit-Project: coreboot
Gerrit-Branch: master
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Gerrit-Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Gerrit-Change-Number: 26659
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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