[coreboot-gerrit] Change in coreboot[master]: mb/technexion: Get rid of whitespace before tab
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon May 28 13:50:25 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26638
Change subject: mb/technexion: Get rid of whitespace before tab
......................................................................
mb/technexion: Get rid of whitespace before tab
Change-Id: Ib2bd31e359ac43bd2215af0af233f92d07685e2f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/technexion/tim5690/devicetree.cb
M src/mainboard/technexion/tim5690/dsdt.asl
M src/mainboard/technexion/tim8690/devicetree.cb
M src/mainboard/technexion/tim8690/dsdt.asl
4 files changed, 42 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26638/1
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb
index bf462e2..e0a8565 100644
--- a/src/mainboard/technexion/tim5690/devicetree.cb
+++ b/src/mainboard/technexion/tim5690/devicetree.cb
@@ -19,7 +19,7 @@
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
+ device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
device pci 5.0 on end # Internal Graphics 0x791F
end
@@ -48,7 +48,7 @@
device pci 13.3 on end # USB 0x438a
device pci 13.4 on end # USB 0x438b
device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
+ device pci 14.0 on # SM 0x4385
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl
index 44da647..ff867cb 100644
--- a/src/mainboard/technexion/tim5690/dsdt.asl
+++ b/src/mainboard/technexion/tim5690/dsdt.asl
@@ -198,9 +198,9 @@
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -799,7 +799,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -815,13 +815,13 @@
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -988,7 +988,7 @@
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1011,19 +1011,19 @@
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1035,7 +1035,7 @@
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1052,7 +1052,7 @@
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1083,7 +1083,7 @@
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1093,7 +1093,7 @@
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1462,7 +1462,7 @@
)
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@@ -1576,7 +1576,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
index 8d1df8b..b7b6f97 100644
--- a/src/mainboard/technexion/tim8690/devicetree.cb
+++ b/src/mainboard/technexion/tim8690/devicetree.cb
@@ -19,7 +19,7 @@
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
chip southbridge/amd/rs690
- device pci 0.0 on end # HT 0x7910
+ device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
device pci 5.0 on end # Internal Graphics 0x791F
end
@@ -48,7 +48,7 @@
device pci 13.3 on end # USB 0x438a
device pci 13.4 on end # USB 0x438b
device pci 13.5 on end # USB 2 0x4386
- device pci 14.0 on # SM 0x4385
+ device pci 14.0 on # SM 0x4385
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl
index ae82a2a..2b22215 100644
--- a/src/mainboard/technexion/tim8690/dsdt.asl
+++ b/src/mainboard/technexion/tim8690/dsdt.asl
@@ -198,9 +198,9 @@
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -799,7 +799,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -815,13 +815,13 @@
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -988,7 +988,7 @@
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1011,19 +1011,19 @@
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1035,7 +1035,7 @@
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1052,7 +1052,7 @@
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1083,7 +1083,7 @@
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1093,7 +1093,7 @@
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1462,7 +1462,7 @@
)
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@@ -1576,7 +1576,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib2bd31e359ac43bd2215af0af233f92d07685e2f
Gerrit-Change-Number: 26638
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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