[coreboot-gerrit] Change in coreboot[master]: src/southbridge: Get rid of whitespace befor tab

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26604 )

Change subject: src/southbridge: Get rid of whitespace befor tab
......................................................................


Patch Set 1:

(11 comments)

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb800/late.c
File src/southbridge/amd/cimx/sb800/late.c:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb800/late.c@355
PS1, Line 355: 			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb800/late.c@361
PS1, Line 361: 			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb800/late.c@390
PS1, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
Comparisons should place the constant on the right side of the test


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb800/late.c@390
PS1, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
braces {} are not necessary for single statement blocks


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb900/late.c
File src/southbridge/amd/cimx/sb900/late.c:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb900/late.c@383
PS1, Line 383: 			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb900/late.c@390
PS1, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
Comparisons should place the constant on the right side of the test


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/cimx/sb900/late.c@390
PS1, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
braces {} are not necessary for single statement blocks


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs690/rs690.c
File src/southbridge/amd/rs690/rs690.c:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs690/rs690.c@92
PS1, Line 92: 	/* CLKCFG:0xE8 Bit[17] = 0x1	 Powerdown clock to IOC GFX block in no external graphics mode */
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs780/gfx.c
File src/southbridge/amd/rs780/gfx.c:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs780/gfx.c@455
PS1, Line 455: 	vgainfo.ulBootUpEngineClock = 500 * 100;		// setup option on reference BIOS, 500 is default
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs780/rs780.c
File src/southbridge/amd/rs780/rs780.c:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/rs780/rs780.c@96
PS1, Line 96: 	/* CLKCFG:0xE8 Bit[17] = 0x1	 Powerdown clock to IOC GFX block in no external graphics mode */
line over 80 characters


https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/sr5650/cmn.h
File src/southbridge/amd/sr5650/cmn.h:

https://review.coreboot.org/#/c/26604/1/src/southbridge/amd/sr5650/cmn.h@23
PS1, Line 23: #define NBHTIU_INDEX	0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
line over 80 characters



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I9a2eada93f05b6a4adac3406c33b6e109b733324
Gerrit-Change-Number: 26604
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Mon, 28 May 2018 09:39:45 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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