[coreboot-gerrit] Change in coreboot[master]: arch/x86: Introduce postcar_frame_add_romcache()

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/26577


Change subject: arch/x86: Introduce postcar_frame_add_romcache()
......................................................................

arch/x86: Introduce postcar_frame_add_romcache()

Provide a common implementation to add an MTRR entry for memory-
mapped boot ROMs.

Change-Id: I9fabc6b87fb36dc3d970805eb804cd950b8849d4
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/arch/x86/include/arch/cpu.h
1 file changed, 13 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/26577/1

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5d44aae..beef70a 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <rules.h>
+#include <cpu/x86/mtrr.h>
 
 /*
  * EFLAGS bits
@@ -283,6 +284,18 @@
 				uintptr_t addr, size_t size, int type);
 
 /*
+ * Add variable MTRR covering the memory-mapped ROM with given MTRR type.
+ */
+static inline void postcar_frame_add_romcache(
+		struct postcar_frame *pcf, int type)
+{
+	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) {
+		postcar_frame_add_mtrr(
+			pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+	}
+}
+
+/*
  * Push used MTRR and Max MTRRs on to the stack
  * and return pointer to stack top.
  */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9fabc6b87fb36dc3d970805eb804cd950b8849d4
Gerrit-Change-Number: 26577
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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