[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/26567


Change subject: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB
......................................................................

cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.

Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/include/cpu/x86/mtrr.h
1 file changed, 14 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/26567/1

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index ad0e5d6..aa67033 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -1,6 +1,8 @@
 #ifndef CPU_X86_MTRR_H
 #define CPU_X86_MTRR_H
 
+#include <commonlib/helpers.h>
+
 /*  These are the region types  */
 #define MTRR_TYPE_UNCACHEABLE		0
 #define MTRR_TYPE_WRCOMB		1
@@ -149,12 +151,20 @@
 /* Make sure it doesn't overlap CAR, though. */
 #define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
 #if CAR_END >= OPTIMAL_CACHE_ROM_BASE
-# define CACHE_ROM_SIZE (_ALIGN_UP_POW2(FROM_TOP(CAR_END)) / 2)
+# define CAR_CACHE_ROM_SIZE (_ALIGN_UP_POW2(FROM_TOP(CAR_END)) / 2)
 #else
-# define CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE
+# define CAR_CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE
 #endif
-#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0)
-# error "CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."
+#if ((CAR_CACHE_ROM_SIZE & (CAR_CACHE_ROM_SIZE-1)) != 0)
+# error "CAR CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."
+#endif
+
+/* Last but not least, most (if not all) chipsets have MMIO
+   between 0xfe000000 and 0xff000000, so limit to 16MiB. */
+#if 16 * MiB < CAR_CACHE_ROM_SIZE
+# define CACHE_ROM_SIZE (16 * MiB)
+#else
+# define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE
 #endif
 
 #define CACHE_ROM_BASE FROM_TOP(CACHE_ROM_SIZE)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Gerrit-Change-Number: 26567
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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