[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/intel/x4x: Limit the DDR3 dram frequency to 400MHz

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26511


Change subject: [WIP]nb/intel/x4x: Limit the DDR3 dram frequency to 400MHz
......................................................................

[WIP]nb/intel/x4x: Limit the DDR3 dram frequency to 400MHz

At 533MHz the display output seems to be broken even though memtest86+
seems to work properly.

Change-Id: I15d62d89e4096eb59435c063ccc63bcb9dd54376
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit.c
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/26511/1

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9e649b0..d031739 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -307,6 +307,8 @@
 			"as last resort");
 		min_tCLK = TCK_400MHZ;
 	}
+	/* FIXME: there seem to be issues with higher frequency */
+	min_tCLK = TCK_400MHZ;
 
 	while (1) {
 		normalize_tCLK(&min_tCLK);

-- 
To view, visit https://review.coreboot.org/26511
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I15d62d89e4096eb59435c063ccc63bcb9dd54376
Gerrit-Change-Number: 26511
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180524/a925cdec/attachment.html>