[coreboot-gerrit] Change in coreboot[master]: mb/google/fizz: Add USB port info

[Emil Lundmark (Code Review)]

Emil Lundmark has uploaded this change for review. ( https://review.coreboot.org/26472


Change subject: mb/google/fizz: Add USB port info
......................................................................

mb/google/fizz: Add USB port info

This adds information about all visible USB ports. Additionally, it
adds _PS0 and _PS3 methods for the USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.

Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk at chromium.org>
---
A src/mainboard/google/fizz/acpi/usb.asl
M src/mainboard/google/fizz/dsdt.asl
2 files changed, 278 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/26472/1

diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl
new file mode 100644
index 0000000..2d9c9ec
--- /dev/null
+++ b/src/mainboard/google/fizz/acpi/usb.asl
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS01)
+{
+	/* USB-C Rear Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS02)
+{
+	/* USB-A Rear Right Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+	/* D0 state - VBUS is on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (2)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (2)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS03)
+{
+	/* USB-A Front Right Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (3)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (3)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS04)
+{
+	/* USB-A Front Left Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (4)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (4)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS05)
+{
+	/* USB-A Rear Left Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (0)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (0)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS06)
+{
+	/* USB-A Rear Middle Port USB 2.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		Zero,	/* USB Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* Visible */
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (1)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (1)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS01)
+{
+	/* USB-C Rear Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS02)
+{
+	/* USB-A Rear Right Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (2)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (2)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS03)
+{
+	/* USB-A Front Right Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (3)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (3)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS04)
+{
+	/* USB-A Front Left Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (4)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (4)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS05)
+{
+	/* USB-A Rear Left Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (0)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (0)
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS06)
+{
+	/* USB-A Rear Middle Port USB 3.0 */
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	/* Connectable */
+		0x03,	/* USB 3.0 Port */
+		Zero,	/* Reserved */
+		Zero	/* Reserved */
+	})
+	/* D0 state - VBUS on */
+	Method (_PS0)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPS (1)
+	}
+	/* D3 state - VBUS off */
+	Method (_PS3)
+	{
+		\_SB.PCI0.LPCB.EC0.UPPC (1)
+	}
+}
diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl
index 24abfc1..69d9158 100644
--- a/src/mainboard/google/fizz/dsdt.asl
+++ b/src/mainboard/google/fizz/dsdt.asl
@@ -67,4 +67,7 @@
 		/* Dynamic Platform Thermal Framework */
 		#include "acpi/dptf.asl"
 	}
+
+	/* USB port entries */
+	#include "acpi/usb.asl"
 }

-- 
To view, visit https://review.coreboot.org/26472
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Gerrit-Change-Number: 26472
Gerrit-PatchSet: 1
Gerrit-Owner: Emil Lundmark <lndmrk at chromium.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180522/ae737a62/attachment-0001.html>