[coreboot-gerrit] Change in coreboot[master]: chromeec: Add support for controlling USB port power

[Emil Lundmark (Code Review)]

Emil Lundmark has uploaded this change for review. ( https://review.coreboot.org/26471


Change subject: chromeec: Add support for controlling USB port power
......................................................................

chromeec: Add support for controlling USB port power

This maps a bit field to the EC that can be used to control the power
state of up to 8 individual USB ports. Some Chromeboxes have their
GPIO pins for controlling USB port power wired to the EC, so they
cannot be accessed by coreboot.

Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Signed-off-by: Emil Lundmark <lndmrk at chromium.org>
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 19 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/26471/1

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index ac4ceb1..f55990e 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -91,6 +91,7 @@
 		Offset (0x0e),
 		Offset (0x12),
 		BTID, 8,	// Battery index that host wants to read
+		USPP, 8,	// USB Port Power
 }
 
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
@@ -512,6 +513,24 @@
 		Return (^TBMD)
 	}
 
+	/*
+	 * Enable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPS, 1, Serialized)
+	{
+		Or (USPP, ShiftLeft (1, Arg0), USPP)
+	}
+
+	/*
+	 * Disable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPC, 1, Serialized)
+	{
+		And (USPP, Not (ShiftLeft (1, Arg0)), USPP)
+	}
+
 	#include "ac.asl"
 	#include "battery.asl"
 	#include "cros_ec.asl"

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Gerrit-Change-Number: 26471
Gerrit-PatchSet: 1
Gerrit-Owner: Emil Lundmark <lndmrk at chromium.org>
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