[coreboot-gerrit] Change in coreboot[master]: nb/amd/amdk8: Get rid of device_t

Elyes HAOUAS (Code Review) gerrit at coreboot.org
Sun May 20 11:35:27 CEST 2018


Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26427


Change subject: nb/amd/amdk8: Get rid of device_t
......................................................................

nb/amd/amdk8: Get rid of device_t

Use of device_t has been abandoned in ramstage.

Change-Id: If540a8b0afb93c1ba8e901c4771228a43c1e6a14
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/amd/amdk8/acpi.c
M src/northbridge/amd/amdk8/acpi.h
M src/northbridge/amd/amdk8/get_sblk_pci1234.c
M src/northbridge/amd/amdk8/misc_control.c
M src/northbridge/amd/amdk8/northbridge.c
M src/northbridge/amd/amdk8/northbridge.h
M src/northbridge/amd/amdk8/raminit_test.c
M src/northbridge/amd/amdk8/util.c
8 files changed, 57 insertions(+), 57 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/26427/1

diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c
index 2fbe7aa..0d42911 100644
--- a/src/northbridge/amd/amdk8/acpi.c
+++ b/src/northbridge/amd/amdk8/acpi.c
@@ -33,7 +33,7 @@
 
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
 {
-	device_t cpu;
+	struct device *cpu;
 	int cpu_index = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
@@ -52,7 +52,7 @@
 
 unsigned long acpi_create_srat_lapics(unsigned long current)
 {
-	device_t cpu;
+	struct device *cpu;
 	int cpu_index = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
@@ -171,7 +171,7 @@
 }
 
 unsigned long northbridge_write_acpi_tables(
-		device_t device,
+		struct device *device,
 		unsigned long start,
 		acpi_rsdp_t *rsdp)
 {
@@ -230,7 +230,7 @@
 }
 
 static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
-	device_t dev;
+	struct device *dev;
 	uint32_t dword;
 	int i;
 
@@ -246,7 +246,7 @@
 	acpigen_pop_len();
 }
 
-void k8acpi_write_vars(device_t device)
+void k8acpi_write_vars(struct device *device)
 {
 	/*
 	 * If more than one physical CPU is installed k8acpi_write_vars()
diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h
index 80e88c1..f8605c6 100644
--- a/src/northbridge/amd/amdk8/acpi.h
+++ b/src/northbridge/amd/amdk8/acpi.h
@@ -17,7 +17,7 @@
 #define AMDK8_ACPI_H
 #include <arch/acpigen.h>
 
-void k8acpi_write_vars(device_t device);
-unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp);
+void k8acpi_write_vars(struct device *device);
+unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp);
 
 #endif
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 1343ae4..fd9584f 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -142,7 +142,7 @@
 void get_sblk_pci1234(void)
 {
 
-	device_t dev;
+	struct device *dev;
 	int i,j;
 	uint32_t dword;
 
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index c472edf..9d2270d 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -35,7 +35,7 @@
  * implemented in a way to NOT DOING legacy VGA resource allocation on
  * purpose :-(.
  */
-static void mcf3_read_resources(device_t dev)
+static void mcf3_read_resources(struct device *dev)
 {
 	struct resource *resource;
 	unsigned char iommu;
@@ -61,13 +61,13 @@
 	}
 }
 
-static void set_agp_aperture(device_t dev)
+static void set_agp_aperture(struct device *dev)
 {
 	struct resource *resource;
 
 	resource = probe_resource(dev, 0x94);
 	if (resource) {
-		device_t pdev;
+		struct device *pdev;
 		uint32_t gart_base, gart_acr;
 
 		/* Remember this resource has been stored */
@@ -97,7 +97,7 @@
 	}
 }
 
-static void mcf3_set_resources(device_t dev)
+static void mcf3_set_resources(struct device *dev)
 {
 	/* Set the gart apeture */
 	set_agp_aperture(dev);
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 0a16db4..d22c3c9 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -40,8 +40,8 @@
 struct amdk8_sysconf_t sysconf;
 
 #define MAX_FX_DEVS 8
-static device_t __f0_dev[MAX_FX_DEVS];
-static device_t __f1_dev[MAX_FX_DEVS];
+static struct device *__f0_dev[MAX_FX_DEVS];
+static struct device *__f1_dev[MAX_FX_DEVS];
 static unsigned fx_devs = 0;
 
 static void get_fx_devs(void)
@@ -71,7 +71,7 @@
 	if (fx_devs == 0)
 		get_fx_devs();
 	for (i = 0; i < fx_devs; i++) {
-		device_t dev;
+		struct device *dev;
 		dev = __f1_dev[i];
 		if (dev && dev->enabled) {
 			pci_write_config32(dev, reg, value);
@@ -127,7 +127,7 @@
 	}
 }
 
-static u32 amdk8_nodeid(device_t dev)
+static u32 amdk8_nodeid(struct device *dev)
 {
 	return (dev->path.pci.devfn >> 3) - 0x18;
 }
@@ -245,7 +245,7 @@
 	}
 }
 
-static void amdk8_scan_chains(device_t dev)
+static void amdk8_scan_chains(struct device *dev)
 {
 	struct bus *link;
 
@@ -258,7 +258,7 @@
 }
 
 
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
 			unsigned goal_link)
 {
 	struct resource *res;
@@ -266,7 +266,7 @@
 	int result;
 	res = 0;
 	for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
-		device_t dev;
+		struct device *dev;
 		dev = __f0_dev[nodeid];
 		if (!dev)
 			continue;
@@ -286,7 +286,7 @@
 	return result;
 }
 
-static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
+static unsigned amdk8_find_reg(struct device *dev, unsigned nodeid, unsigned link,
 			       unsigned min, unsigned max)
 {
 	unsigned resource;
@@ -314,17 +314,17 @@
 	return resource;
 }
 
-static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
 {
 	return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
 }
 
-static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_mempair(struct device *dev, unsigned nodeid, unsigned link)
 {
 	return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
 }
 
-static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
+static void amdk8_link_read_bases(struct device *dev, unsigned nodeid, unsigned link)
 {
 	struct resource *resource;
 
@@ -363,9 +363,9 @@
 	}
 }
 
-static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
+static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid);
 
-static void amdk8_read_resources(device_t dev)
+static void amdk8_read_resources(struct device *dev)
 {
 	unsigned nodeid;
 	struct bus *link;
@@ -378,7 +378,7 @@
 	amdk8_create_vga_resource(dev, nodeid);
 }
 
-static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
+static void amdk8_set_resource(struct device *dev, struct resource *resource, unsigned nodeid)
 {
 	struct bus *link;
 	resource_t rbase, rend;
@@ -475,7 +475,7 @@
 	report_resource_stored(dev, resource, buf);
 }
 
-static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
+static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid)
 {
 	struct resource *resource;
 	struct bus *link;
@@ -485,7 +485,7 @@
 	for (link = dev->link_list; link; link = link->next) {
 		if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
-			extern device_t vga_pri; // the primary vga device, defined in device.c
+			extern struct device *vga_pri; // the primary vga device, defined in device.c
 			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
 				link->secondary,link->subordinate);
 			/* We need to make sure the vga_pri is under the link */
@@ -516,7 +516,7 @@
 			  IORESOURCE_ASSIGNED;
 }
 
-static void amdk8_set_resources(device_t dev)
+static void amdk8_set_resources(struct device *dev)
 {
 	unsigned nodeid;
 	struct bus *bus;
@@ -597,7 +597,7 @@
 	.init = amdk8_nb_init,
 };
 
-static void amdk8_domain_read_resources(device_t dev)
+static void amdk8_domain_read_resources(struct device *dev)
 {
 	unsigned reg;
 
@@ -610,7 +610,7 @@
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
 			unsigned nodeid, reg_link;
-			device_t reg_dev;
+			struct device *reg_dev;
 			nodeid = limit & 7;
 			reg_link = (limit >> 4) & 3;
 			reg_dev = __f0_dev[nodeid];
@@ -717,7 +717,7 @@
 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 {
 	int i;
-	device_t dev;
+	struct device *dev;
 	u32 base, limit;
 	u32 hoist;
 	u32 hole_sizek;
@@ -762,7 +762,7 @@
 {
 	int i;
 	u32 carry_over;
-	device_t dev;
+	struct device *dev;
 	u32 base, limit;
 	u32 basek;
 	u32 hoist;
@@ -857,7 +857,7 @@
 #endif
 }
 
-static void amdk8_domain_set_resources(device_t dev)
+static void amdk8_domain_set_resources(struct device *dev)
 {
 	unsigned long mmio_basek;
 	u32 pci_tolm;
@@ -1009,7 +1009,7 @@
 
 }
 
-static void amdk8_domain_scan_bus(device_t dev)
+static void amdk8_domain_scan_bus(struct device *dev)
 {
 	u32 reg;
 	int i;
@@ -1029,7 +1029,7 @@
 	 */
 	get_fx_devs();
 	for (i = 0; i < fx_devs; i++) {
-		device_t f0_dev;
+		struct device *f0_dev;
 		f0_dev = __f0_dev[i];
 		if (f0_dev && f0_dev->enabled) {
 			u32 httc;
@@ -1055,7 +1055,7 @@
 	.scan_bus	  = amdk8_domain_scan_bus,
 };
 
-static void add_more_links(device_t dev, unsigned total_links)
+static void add_more_links(struct device *dev, unsigned total_links)
 {
 	struct bus *link, *last = NULL;
 	int link_num = -1;
@@ -1095,7 +1095,7 @@
 static void remap_bsp_lapic(struct bus *cpu_bus)
 {
 	struct device_path cpu_path;
-	device_t cpu;
+	struct device *cpu;
 	u32 bsp_lapic_id = lapicid();
 
 	if (bsp_lapic_id) {
@@ -1107,10 +1107,10 @@
 	}
 }
 
-static void cpu_bus_scan(device_t dev)
+static void cpu_bus_scan(struct device *dev)
 {
 	struct bus *cpu_bus;
-	device_t dev_mc;
+	struct device *dev_mc;
 	int bsp_apicid;
 	int i,j;
 	unsigned nb_cfg_54;
@@ -1165,7 +1165,7 @@
 	remap_bsp_lapic(cpu_bus);
 
 	for (i = 0; i < sysconf.nodes; i++) {
-		device_t cpu_dev;
+		struct device *cpu_dev;
 
 		/* Find the cpu's pci device */
 		cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
@@ -1174,7 +1174,7 @@
 			 * ensure all of the cpu's pci devices are found.
 			 */
 			int local_j;
-			device_t dev_f0;
+			struct device *dev_f0;
 			for (local_j = 0; local_j <= 3; local_j++) {
 				cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
 					PCI_DEVFN(0x18 + i, local_j));
@@ -1241,14 +1241,14 @@
 				}
 			}
 
-			device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
+			struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
 			if (cpu)
 				amd_cpu_topology(cpu, i, j);
 		} //j
 	}
 }
 
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
 {
 #if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT)
 	cpus_ready_for_init();
diff --git a/src/northbridge/amd/amdk8/northbridge.h b/src/northbridge/amd/amdk8/northbridge.h
index b39a594..99bfe4f 100644
--- a/src/northbridge/amd/amdk8/northbridge.h
+++ b/src/northbridge/amd/amdk8/northbridge.h
@@ -1,6 +1,6 @@
 #ifndef NORTHBRIDGE_AMD_AMDK8_H
 #define NORTHBRIDGE_AMD_AMDK8_H
 
-extern unsigned int amdk8_scan_root_bus(device_t root, unsigned int max);
+extern unsigned int amdk8_scan_root_bus(struct device *root, unsigned int max);
 
 #endif /* NORTHBRIDGE_AMD_AMDK8_H */
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index a17f197..215a537 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -33,21 +33,21 @@
 
 unsigned char pci_register[256*5*3*256];
 
-static uint8_t pci_read_config8(device_t dev, unsigned where)
+static uint8_t pci_read_config8(struct device *dev, unsigned where)
 {
 	unsigned addr;
 	addr = dev | where;
 	return pci_register[addr];
 }
 
-static uint16_t pci_read_config16(device_t dev, unsigned where)
+static uint16_t pci_read_config16(struct device *dev, unsigned where)
 {
 	unsigned addr;
 	addr = dev | where;
 	return pci_register[addr] | (pci_register[addr + 1]  << 8);
 }
 
-static uint32_t pci_read_config32(device_t dev, unsigned where)
+static uint32_t pci_read_config32(struct device *dev, unsigned where)
 {
 	unsigned addr;
 	uint32_t value;
@@ -60,14 +60,14 @@
 
 }
 
-static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
+static void pci_write_config8(struct device *dev, unsigned where, uint8_t value)
 {
 	unsigned addr;
 	addr = dev | where;
 	pci_register[addr] = value;
 }
 
-static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
+static void pci_write_config16(struct device *dev, unsigned where, uint16_t value)
 {
 	unsigned addr;
 	addr = dev | where;
@@ -75,7 +75,7 @@
 	pci_register[addr + 1] = (value >> 8) & 0xff;
 }
 
-static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
+static void pci_write_config32(struct device *dev, unsigned where, uint32_t value)
 {
 	unsigned addr;
 	addr = dev | where;
@@ -86,7 +86,7 @@
 }
 
 #define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device(unsigned pci_id, device_t dev)
+static struct device *pci_locate_device(unsigned pci_id, struct device *dev)
 {
 	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
diff --git a/src/northbridge/amd/amdk8/util.c b/src/northbridge/amd/amdk8/util.c
index b701c7f..aea0469 100644
--- a/src/northbridge/amd/amdk8/util.c
+++ b/src/northbridge/amd/amdk8/util.c
@@ -189,7 +189,7 @@
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showalldram(int level, device_t dev)
+static void showalldram(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
@@ -207,7 +207,7 @@
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallmmio(int level, device_t dev)
+static void showallmmio(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
@@ -225,7 +225,7 @@
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallpciio(int level, device_t dev)
+static void showallpciio(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
@@ -243,7 +243,7 @@
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallconfig(int level, device_t dev)
+static void showallconfig(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
@@ -260,7 +260,7 @@
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-void showallroutes(int level, device_t dev)
+void showallroutes(int level, struct device *dev)
 {
 	showalldram(level, dev);
 	showallmmio(level, dev);

-- 
To view, visit https://review.coreboot.org/26427
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If540a8b0afb93c1ba8e901c4771228a43c1e6a14
Gerrit-Change-Number: 26427
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180520/353080eb/attachment-0001.html>


More information about the coreboot-gerrit mailing list