[coreboot-gerrit] Change in coreboot[master]: nb/via/vx900: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 20 11:04:24 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26426
Change subject: nb/via/vx900: Get rid of device_t
......................................................................
nb/via/vx900: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Id6323843b4f929e5f9551f86dd1305ab716ea7ac
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/via/vx900/chrome9hd.c
M src/northbridge/via/vx900/lpc.c
M src/northbridge/via/vx900/northbridge.c
M src/northbridge/via/vx900/pci_util.c
M src/northbridge/via/vx900/pcie.c
M src/northbridge/via/vx900/sata.c
M src/northbridge/via/vx900/traf_ctrl.c
M src/northbridge/via/vx900/vx900.h
8 files changed, 49 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26426/1
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 00b5c4b..fb5841e 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -98,7 +98,7 @@
u8 vx900_int15_get_5f18_bl(void)
{
u8 reg8, ret;
- device_t dev;
+ struct device *dev;
/*
* BL Bit[7:4]
* Memory Data Rate (not to be confused with fCLK)
@@ -137,7 +137,7 @@
vga_sr_write(0x37, device & 0xff); /* SID low byte */
}
-static void chrome9hd_handle_uma(device_t dev)
+static void chrome9hd_handle_uma(struct device *dev)
{
u8 fb_pow = vx900_get_chrome9hd_fb_pow();
@@ -165,11 +165,11 @@
*
* This document is only available under NDA.
*/
-static void chrome9hd_biosguide_init_seq(device_t dev)
+static void chrome9hd_biosguide_init_seq(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
- device_t host = dev_find_device(PCI_VENDOR_ID_VIA,
+ struct device *host = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
/* Step 1 - Enable VGA controller */
@@ -208,7 +208,7 @@
}
-static void chrome9hd_init(device_t dev)
+static void chrome9hd_init(struct device *dev)
{
printk(BIOS_DEBUG, "======================================================\n");
printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
@@ -243,17 +243,17 @@
dump_pci_device(dev);
}
-static void chrome9hd_enable(device_t dev)
+static void chrome9hd_enable(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* FIXME: here? -=- ACLK 250MHz */
pci_mod_config8(mcu, 0xbb, 0, 0x01);
}
-static void chrome9hd_disable(device_t dev)
+static void chrome9hd_disable(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* Disable GFX - This step effectively renders the GFX inert
* It won't even show up as a PCI device during enumeration */
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 43e4d4c..075a872 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -47,7 +47,7 @@
* it will work, but perhaps this should be more configurable.
*/
-static void vx900_lpc_misc_stuff(device_t dev)
+static void vx900_lpc_misc_stuff(struct device *dev)
{
char extint;
u8 val;
@@ -71,7 +71,7 @@
}
}
-static void vx900_lpc_dma_setup(device_t dev)
+static void vx900_lpc_dma_setup(struct device *dev)
{
/* These are the steps recommended by VIA in order to get DMA running */
@@ -104,12 +104,12 @@
* We are assuming this is called before the drivers/generic/ioapic code,
* which should be the case if devicetree.cb is set up properly.
*/
-static void vx900_lpc_ioapic_setup(device_t dev)
+static void vx900_lpc_ioapic_setup(struct device *dev)
{
/* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
* If it's not, then the generic ioapic driver will not set it up
* correctly, and the MP table will not be correctly generated */
- device_t ioapic;
+ struct device *ioapic;
for (ioapic = dev->next; ioapic; ioapic = ioapic->next) {
if (ioapic->path.type == DEVICE_PATH_IOAPIC)
break;
@@ -151,7 +151,7 @@
pci_mod_config8(dev, 0x58, 0, 1 << 6);
}
-static void vx900_lpc_interrupt_stuff(device_t dev)
+static void vx900_lpc_interrupt_stuff(struct device *dev)
{
/* Enable setting trigger mode through 0x4d0, and 0x4d1 ports
* And enable I/O recovery time */
@@ -177,14 +177,14 @@
vx900_lpc_ioapic_setup(dev);
}
-static void vx900_lpc_init(device_t dev)
+static void vx900_lpc_init(struct device *dev)
{
vx900_lpc_interrupt_stuff(dev);
vx900_lpc_misc_stuff(dev);
dump_pci_device(dev);
}
-static void vx900_lpc_read_resources(device_t dev)
+static void vx900_lpc_read_resources(struct device *dev)
{
struct resource *res;
pci_dev_read_resources(dev);
@@ -206,7 +206,7 @@
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
}
-static void vx900_lpc_set_resources(device_t dev)
+static void vx900_lpc_set_resources(struct device *dev)
{
struct resource *mmio, *spi;
u32 reg;
@@ -248,7 +248,7 @@
#if IS_ENABLED(CONFIG_PIRQ_ROUTE)
void pirq_assign_irqs(const u8 * pirq)
{
- device_t lpc;
+ struct device *lpc;
lpc = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_LPC, 0);
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 3f839c7..6c221ae 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -57,7 +57,7 @@
return uma_memory_base;
}
-static u64 vx900_get_top_of_ram(device_t mcu)
+static u64 vx900_get_top_of_ram(struct device *mcu)
{
u16 reg16;
/* The last valid DRAM address is computed by the MCU
@@ -94,7 +94,7 @@
*
* @return The new top of memory.
*/
-static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
+static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm)
{
size_t i;
u8 reg8, start8, end8, start, end;
@@ -214,7 +214,7 @@
return newtor;
}
-static void vx900_set_resources(device_t dev)
+static void vx900_set_resources(struct device *dev)
{
u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
@@ -226,7 +226,7 @@
"========================================\n");
int idx = 10;
- const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ const struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
0);
if (!mcu) {
@@ -283,7 +283,7 @@
assign_resources(dev->link_list);
}
-static void vx900_read_resources(device_t dev)
+static void vx900_read_resources(struct device *dev)
{
/* Our fixed resources start at 0 */
int idx = 0;
@@ -310,7 +310,7 @@
.scan_bus = pci_domain_scan_bus,
};
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
}
@@ -323,7 +323,7 @@
.scan_bus = 0,
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c
index 1674e85..e0ef3da 100644
--- a/src/northbridge/via/vx900/pci_util.c
+++ b/src/northbridge/via/vx900/pci_util.c
@@ -16,7 +16,7 @@
#include "vx900.h"
-void dump_pci_device(device_t dev)
+void dump_pci_device(struct device *dev)
{
int i;
for (i = 0; i <= 0xff; i++) {
@@ -35,7 +35,7 @@
}
}
-void pci_mod_config8(device_t dev, unsigned int where,
+void pci_mod_config8(struct device *dev, unsigned int where,
uint8_t clr_mask, uint8_t set_mask)
{
uint8_t reg8 = pci_read_config8(dev, where);
@@ -44,7 +44,7 @@
pci_write_config8(dev, where, reg8);
}
-void pci_mod_config16(device_t dev, unsigned int where,
+void pci_mod_config16(struct device *dev, unsigned int where,
uint16_t clr_mask, uint16_t set_mask)
{
uint16_t reg16 = pci_read_config16(dev, where);
@@ -53,7 +53,7 @@
pci_write_config16(dev, where, reg16);
}
-void pci_mod_config32(device_t dev, unsigned int where,
+void pci_mod_config32(struct device *dev, unsigned int where,
uint32_t clr_mask, uint32_t set_mask)
{
uint32_t reg32 = pci_read_config32(dev, where);
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index ae81739..1d3ecd9 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -35,7 +35,7 @@
* If the link never comes up, we hang.
*/
-static void vx900_pcie_link_init(device_t dev)
+static void vx900_pcie_link_init(struct device *dev)
{
u8 reg8;
u32 reg32;
@@ -81,12 +81,12 @@
* time? */
}
-static void vx900_pex_dev_set_resources(device_t dev)
+static void vx900_pex_dev_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
-static void vx900_pex_init(device_t dev)
+static void vx900_pex_init(struct device *dev)
{
/* FIXME: For some reason, PEX0 hangs on init. Find issue, fix it. */
if ((dev->path.pci.devfn & 0x7) == 0)
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index e0a54bd..4df0053 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -71,7 +71,7 @@
printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");
}
-static void vx900_dbg_sata_errors(device_t dev)
+static void vx900_dbg_sata_errors(struct device *dev)
{
/* Port 0 */
if (pci_read_config8(dev, 0xa0) & (1 << 0)) {
@@ -100,7 +100,7 @@
0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
-static u32 sata_phy_read32(device_t dev, u8 index)
+static u32 sata_phy_read32(struct device *dev, u8 index)
{
/* The SATA PHY control registers are accessed by a funny index/value
* scheme. Each byte (0,1,2,3) has its own 4-bit index */
@@ -112,7 +112,7 @@
return pci_read_config32(dev, 0x64);
}
-static void sata_phy_write32(device_t dev, u8 index, u32 val)
+static void sata_phy_write32(struct device *dev, u8 index, u32 val)
{
/* The SATA PHY control registers are accessed by a funny index/value
* scheme. Each byte (0,1,2,3) has its own 4-bit index */
@@ -124,7 +124,7 @@
pci_write_config32(dev, 0x64, val);
}
-static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg)
+static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg)
{
size_t i;
u32 *data = (u32 *) cfg;
@@ -133,7 +133,7 @@
}
}
-static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
+static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg)
{
size_t i;
u32 *data = (u32 *) cfg;
@@ -175,7 +175,7 @@
* Our only option is to operate in IDE mode. We choose native IDE so that we
* can freely assign an IRQ, and are not forced to use IRQ14
*/
-static void vx900_native_ide_mode(device_t dev)
+static void vx900_native_ide_mode(struct device *dev)
{
/* Disable subclass write protect */
pci_mod_config8(dev, 0x45, 1 << 7, 0);
@@ -187,7 +187,7 @@
pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
}
-static void vx900_sata_init(device_t dev)
+static void vx900_sata_init(struct device *dev)
{
/* Enable SATA primary channel IO access */
pci_mod_config8(dev, 0x40, 0, 1 << 1);
@@ -255,7 +255,7 @@
vx900_dbg_sata_errors(dev);
}
-static void vx900_sata_read_resources(device_t dev)
+static void vx900_sata_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
}
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 0fb55b3..8bdf25c 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -45,10 +45,10 @@
* We are assuming this is called before the drivers/generic/ioapic code,
* which should be the case if devicetree.cb is set up properly.
*/
-static void vx900_north_ioapic_setup(device_t dev)
+static void vx900_north_ioapic_setup(struct device *dev)
{
u8 base_val;
- device_t ioapic;
+ struct device *ioapic;
ioapic_config_t *config;
/* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
* If it's not, then the generic ioapic driver will not set it up
@@ -103,7 +103,7 @@
*
* FIXME: triple-quadruple-check this
*/
-static void vx900_pex_link_setup(device_t dev)
+static void vx900_pex_link_setup(struct device *dev)
{
u8 reg8;
struct northbridge_via_vx900_config *nb = (void *)dev->chip_info;
@@ -120,7 +120,7 @@
pci_write_config8(dev, 0xb0, reg8);
}
-static void vx900_traf_ctr_init(device_t dev)
+static void vx900_traf_ctr_init(struct device *dev)
{
vx900_north_ioapic_setup(dev);
vx900_pex_link_setup(dev);
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
index cb7bca9..a2a360a 100644
--- a/src/northbridge/via/vx900/vx900.h
+++ b/src/northbridge/via/vx900/vx900.h
@@ -50,12 +50,12 @@
void pci_mod_config32(pci_devfn_t dev, unsigned int where,
uint32_t clr_mask, uint32_t set_mask);
#else
-void dump_pci_device(device_t dev);
-void pci_mod_config8(device_t dev, unsigned int where,
+void dump_pci_device(struct device *dev);
+void pci_mod_config8(struct device *dev, unsigned int where,
uint8_t clr_mask, uint8_t set_mask);
-void pci_mod_config16(device_t dev, unsigned int where,
+void pci_mod_config16(struct device *dev, unsigned int where,
uint16_t clr_mask, uint16_t set_mask);
-void pci_mod_config32(device_t dev, unsigned int where,
+void pci_mod_config32(struct device *dev, unsigned int where,
uint32_t clr_mask, uint32_t set_mask);
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id6323843b4f929e5f9551f86dd1305ab716ea7ac
Gerrit-Change-Number: 26426
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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