[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/acpi: Create a GPIO library

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26334


Change subject: soc/amd/stoneyridge/acpi: Create a GPIO library
......................................................................

soc/amd/stoneyridge/acpi: Create a GPIO library

There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.

BUG=b:79546790
TEST=Build grunt

Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
A src/soc/amd/stoneyridge/acpi/gpio_lib.asl
M src/soc/amd/stoneyridge/acpi/soc.asl
2 files changed, 178 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/26334/1

diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
new file mode 100644
index 0000000..979ecd8
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+/* Get pin control MMIO address */
+Method (GPAD, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin number */
+	Add ( Multiply (Arg0, 4), 0x1500, Local1)
+	Add ( AMD_SB_ACPI_MMIO_ADDR, Local1, Local1)
+	Return (Local1)
+}
+
+/* Read pin control dword */
+Method (GPRD, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TEMP, 32
+	}
+	Return (TEMP)
+}
+
+/* Read pin control byte 0 */
+Method (GPR0, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Return (TMP0)
+}
+
+/* Read pin control byte 1 */
+Method (GPR1, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Return (TMP1)
+}
+
+/* Read pin control byte 2 */
+Method (GPR2, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Return (TMP2)
+}
+
+/* Read pin control byte 3 */
+Method (GPR3, 0x1, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Return (TMP3)
+}
+
+/* Write pin control dword */
+Method (GPWR, 0x2, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	/* Arg1 - Value for control register */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TEMP,32
+	}
+	Store (Arg1, TEMP)
+}
+
+/* Write pin control byte 0 */
+Method (GPW0, 0x2, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	/* Arg1 - Value for control register */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Store (Arg1, TMP0)
+}
+
+/* Write pin control byte 1 */
+Method (GPW1, 0x2, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	/* Arg1 - Value for control register */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Store (Arg1, TMP1)
+}
+
+/* Write pin control byte 2 */
+Method (GPW2, 0x2, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	/* Arg1 - Value for control register */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Store (Arg1, TMP2)
+}
+
+/* Write pin control byte 3 */
+Method (GPW3, 0x2, Serialized)
+{
+	/* Arg0 - GPIO pin control MMIO address */
+	/* Arg1 - Value for control register */
+	Store (Arg0, Local0)
+	OperationRegion (GPDW, SystemMemory, Local0, 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve) {
+		TMP0, 8,
+		TMP1, 8,
+		TMP2, 8,
+		TMP3, 8,
+	}
+	Store (Arg1, TMP3)
+}
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
index d777294..9b8773e 100644
--- a/src/soc/amd/stoneyridge/acpi/soc.asl
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -26,3 +26,7 @@
 
 /* Describe the devices in the Southbridge */
 #include "sb_fch.asl"
+
+
+/* Add GPIO library */
+#include <gpio_lib.asl>

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Gerrit-Change-Number: 26334
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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