[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Bypass FSP's memorytest and pcie power sequence.

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/26284


Change subject: soc/intel/apollolake: Bypass FSP's memorytest and pcie power sequence.
......................................................................

soc/intel/apollolake: Bypass FSP's memorytest and pcie power sequence.

        Initialize UPD's in coreboot to skip CpuMemorytest and Pcie power sequence

BUG=b:78599939
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik at intel.com>
---
M src/soc/intel/apollolake/romstage.c
1 file changed, 7 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26284/1

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index bccfc16..2b5b965 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -325,6 +325,13 @@
 	m_cfg->RootPort3Perst = 0;
 	m_cfg->RootPort4Perst = 0;
 	m_cfg->RootPort5Perst = 0;
+
+	/* Initialize below UPD's to skip memory test and pcie power sequence
+	 * in FSP.
+	 */
+	m_cfg->SkipMemoryTestUpd = 1;
+	m_cfg->SkipPciePowerSequence = 1;
+
 #endif
 }
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Gerrit-Change-Number: 26284
Gerrit-PatchSet: 1
Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik at intel.com>
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