[coreboot-gerrit] Change in coreboot[master]: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26275


Change subject: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K
......................................................................

arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K

As per c_start.S implementation logic, struct cpu_info pointer
will be present at 8 bytes below stack_top(_estack).

Getting stack_base and stack_end using checkstack(_estack, 0)
function and comparing struct cpu_info *ci pointer address with
different STACK_SIZE.

STACK_SIZE=8K (0x2000)

stack_base = 0x85ccc000
stack_top = 0x85cce000

(struct cpu_info) ci = 0x85ccdff8

STACK_SIZE=16K (0x4000)

stack_base = 0x85cca000
stack_top = 0x85cce000

(struct cpu_info) ci = 0x85ccfff8

Due to wrong alignment issue, cpu_index variable is getting random/wrong
value.

BUG=b:79562868
TEST=Verify cpu_index is returning correct cpu_index of BSP and AP
with different STACK_SIZE 4K/8K/16K/32K on KBL and CNL platform.

Change-Id: I3ef0590b50ceca36c25198beb6775ae51da6420b
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/Kconfig
M src/arch/x86/c_start.S
M src/arch/x86/include/arch/cpu.h
3 files changed, 8 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/26275/1

diff --git a/src/Kconfig b/src/Kconfig
index 99a704d..73e6fcd 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -395,6 +395,11 @@
 	default 0x1000 if ARCH_X86
 	default 0x0
 
+config STACK_ALIGNMENT_SIZE
+	hex
+	default 0x1000 if ARCH_X86
+	default 0x0
+
 config MAX_CPUS
 	int
 	default 1
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 6426ef3..b9573ba 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -19,7 +19,7 @@
 .global _stack
 .global _estack
 
-.align CONFIG_STACK_SIZE
+.align CONFIG_STACK_ALIGNMENT_SIZE
 _stack:
 .space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE
 _estack:
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5d44aae..7d0f182 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -206,8 +206,8 @@
 		"orl  %2, %0 "
 #endif
 		: "=r" (ci)
-		: "0" (~(CONFIG_STACK_SIZE - 1)),
-		"r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
+		: "0" (~(CONFIG_STACK_ALIGNMENT_SIZE - 1)),
+		"r" (CONFIG_STACK_ALIGNMENT_SIZE - sizeof(struct cpu_info))
 	);
 	return ci;
 }

-- 
To view, visit https://review.coreboot.org/26275
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3ef0590b50ceca36c25198beb6775ae51da6420b
Gerrit-Change-Number: 26275
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180514/00e83ea4/attachment.html>