[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 13 12:49:59 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26245
Change subject: sb/intel/i82801gx: Get rid of device_t
......................................................................
sb/intel/i82801gx: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Iccddf3140fd94c2e5a246fe2839573f5dd387147
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/i82801gx.c
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801gx/watchdog.c
13 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26245/1
diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c
index b86891b..a4f6528 100644
--- a/src/southbridge/intel/i82801gx/ac97.c
+++ b/src/southbridge/intel/i82801gx/ac97.c
@@ -246,7 +246,7 @@
}
}
-static void ac97_set_subsystem(device_t dev, unsigned int vendor,
+static void ac97_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 01c1196..1642504 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -303,7 +303,7 @@
}
}
-static void azalia_set_subsystem(device_t dev, unsigned int vendor,
+static void azalia_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index aab674b..eb0583f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -20,7 +20,7 @@
#include "i82801gx.h"
#include "sata.h"
-void i82801gx_enable(device_t dev)
+void i82801gx_enable(struct device *dev)
{
u32 reg32;
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index df744fc..1038baf 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -44,7 +44,7 @@
#if !defined(__PRE_RAM__)
#include "chip.h"
#if !defined(__SIMPLE_DEVICE__)
-void i82801gx_enable(device_t dev);
+void i82801gx_enable(struct device *dev);
#endif
void gpi_route_interrupt(u8 gpi, u8 mode);
#else
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index e135336..8159570 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -91,7 +91,7 @@
printk(BIOS_DEBUG, "\n");
}
-static void ide_set_subsystem(device_t dev, unsigned int vendor,
+static void ide_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index a26b9f8..462e357 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -88,9 +88,9 @@
* 0x80 - The PIRQ is not routed.
*/
-static void i82801gx_pirq_init(device_t dev)
+static void i82801gx_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -134,7 +134,7 @@
}
}
-static void i82801gx_gpi_routing(device_t dev)
+static void i82801gx_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -163,7 +163,7 @@
pci_write_config32(dev, GPIO_ROUT, reg32);
}
-static void i82801gx_power_options(device_t dev)
+static void i82801gx_power_options(struct device *dev)
{
u8 reg8;
u16 reg16, pmbase;
@@ -267,7 +267,7 @@
outl(reg32, pmbase + 0x04);
}
-static void i82801gx_configure_cstates(device_t dev)
+static void i82801gx_configure_cstates(struct device *dev)
{
u8 reg8;
@@ -487,7 +487,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@@ -603,7 +603,7 @@
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}
-static void i82801gx_lpc_read_resources(device_t dev)
+static void i82801gx_lpc_read_resources(struct device *dev)
{
struct resource *res;
u8 io_index = 0;
@@ -645,7 +645,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned int vendor,
+static void set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
@@ -657,7 +657,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 1635dfe..a054dc4 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -97,7 +97,7 @@
ich_pci_dev_enable_resources(dev);
}
-static void set_subsystem(device_t dev, unsigned int vendor,
+static void set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
/* NOTE: This is not the default position! */
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 0d14ff4..b7a60f2 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -89,7 +89,7 @@
pci_write_config16(dev, 0x1e, reg16);
}
-static void pcie_set_subsystem(device_t dev, unsigned int vendor,
+static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
/* NOTE: This is not the default position! */
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index a08f266..e46ee46 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -199,7 +199,7 @@
pci_write_config32(dev, SATA_IR, reg32);
}
-static void sata_set_subsystem(device_t dev, unsigned int vendor,
+static void sata_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index fdf76a0..63e66d4 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "i82801gx.h"
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -38,7 +38,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@@ -50,7 +50,7 @@
return do_smbus_write_byte(res->base, device, address, data);
}
-static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
+static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf)
{
u16 device;
struct resource *res;
@@ -62,7 +62,7 @@
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
-static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)
+static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
{
u16 device;
struct resource *res;
@@ -82,7 +82,7 @@
.block_write = lsmbus_block_write,
};
-static void smbus_set_subsystem(device_t dev, unsigned int vendor, unsigned int device)
+static void smbus_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -97,7 +97,7 @@
.set_subsystem = smbus_set_subsystem,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
index 2978080..092ca9f 100644
--- a/src/southbridge/intel/i82801gx/usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -42,7 +42,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_set_subsystem(device_t dev, unsigned int vendor,
+static void usb_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 6ed2dcb..e6dd6c9 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -58,7 +58,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c
index 9365e89..ac2de3a 100644
--- a/src/southbridge/intel/i82801gx/watchdog.c
+++ b/src/southbridge/intel/i82801gx/watchdog.c
@@ -22,7 +22,7 @@
void watchdog_off(void)
{
- device_t dev;
+ struct device *dev;
unsigned long value, base;
/* Turn off the ICH7 watchdog. */
--
To view, visit https://review.coreboot.org/26245
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iccddf3140fd94c2e5a246fe2839573f5dd387147
Gerrit-Change-Number: 26245
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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