[coreboot-gerrit] Change in coreboot[master]: grunt: Add agesa performance metrics into cbmem
Raul Rangel (Code Review)
gerrit at coreboot.org
Thu May 10 21:01:53 CEST 2018
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/26220
Change subject: grunt: Add agesa performance metrics into cbmem
......................................................................
grunt: Add agesa performance metrics into cbmem
AGESA provides hooks for extracting performance metrics. It uses the IDS
callout to retrieve a pointer and it then writes TP_Perf_STRUCT.
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file
from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed
everything that we don't need. I did have to change
MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00.
Once the struct has been populated I call timestamp_add for each entry
to add the timestamps to cbmem.
This does not pull out the S3 performance metrics because the IDS bios
callout happens in romstage as part of AmdInitResume. DRAM is up at this
point so I'm sure we could play some tricks if we wanted.
An AGESA binary with IDSOPT_PERF_ANALYSIS enabled must be used to
extract the timestamps.
MAX_TIMESTAMPS must also be increased.
BUG=b:64549506
TEST=boot on grunt and run cbmem -t
0:1st timestamp 22,008
900:calling AmdInitReset 90,894 (68,886)
4396:BeginProcAmdInitReset 92,274 (1,380)
4398:BeginInitReset 93,489 (1,215)
4399:EndInitReset 100,549 (7,060)
4397:EndProcAmdInitReset 100,751 (202)
901:back from AmdInitReset 101,680 (929)
4352:BeginProcAmdInitEarly 101,797 (117)
4354:BeginAmdTopoInitialize 101,890 (93)
4355:EndAmdTopoInitialize 102,259 (369)
4356:BeginGnbInitAtEarlier 102,260 (1)
902:calling AmdInitEarly 102,689 (429)
4438:BeginGnbLoadScsData 107,895 (5,206)
4439:EndGnbLoadScsData 108,833 (938)
4357:EndGnbInitAtEarlier 108,906 (73)
4358:BeginAmdCpuEarly 108,907 (1)
4359:EndAmdCpuEarly 119,701 (10,794)
4360:BeginGnbInitAtEarly 119,881 (180)
4440:BeginGnbPcieTraining 125,608 (5,727)
4441:EndGnbPcieTraining 142,405 (16,797)
4361:EndGnbInitAtEarly 142,488 (83)
4353:EndProcAmdInitEarly 142,509 (21)
903:back from AmdInitEarly 143,537 (1,028)
5:start of verified boot 160,263 (16,726)
...
Change-Id: If8399dd5d69d53ad41834b40d7f06d6b6e0093ad
Signed-off-by: Raul E Rangel <rrangel at chromium.org>
---
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/soc/amd/common/block/include/amdblocks/agesawrapper.h
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/common/block/pi/def_callouts.c
A src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h
M src/vendorcode/amd/pi/00670F00/agesa_headers.h
6 files changed, 254 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/26220/1
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 304e43f..5310a40 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -144,6 +144,12 @@
TS_START_KERNEL = 1101,
TS_KERNEL_DECOMPRESSION = 1102,
+
+ /*
+ * 0x1100 - 0x11FF reserved for AGESA internal IDs.
+ * The values are 0x1000 + the value of the enum defined in IdsPerf.h
+ */
+ TS_AGESA_INTERNAL_START = 0x1100,
};
static const struct timestamp_id_to_name {
@@ -258,6 +264,107 @@
{ TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
{ TS_FSP_AFTER_END_OF_FIRMWARE,
"returning from FspNotify(EndOfFirmware)" },
+
+ /*
+ * TODO(rrangel): Is there an ifdef I can add around this so it only
+ * gets included in the cbmem util and possibly ramstage?
+ */
+
+ /* AMD AGESA internal timestamps. See IdsPerf.h */
+ { 0x1100, "BeginProcAmdInitEarly" },
+ { 0x1101, "EndProcAmdInitEarly" },
+ { 0x1102, "BeginAmdTopoInitialize" },
+ { 0x1103, "EndAmdTopoInitialize" },
+ { 0x1104, "BeginGnbInitAtEarlier" },
+ { 0x1105, "EndGnbInitAtEarlier" },
+ { 0x1106, "BeginAmdCpuEarly" },
+ { 0x1107, "EndAmdCpuEarly" },
+ { 0x1108, "BeginGnbInitAtEarly" },
+ { 0x1109, "EndGnbInitAtEarly" },
+ { 0x110A, "BeginProcAmdInitEnv" },
+ { 0x110B, "EndProcAmdInitEnv" },
+ { 0x110C, "BeginInitEnv" },
+ { 0x110D, "EndInitEnv" },
+ { 0x110E, "BeginGnbInitAtEnv" },
+ { 0x110F, "EndGnbInitAtEnv" },
+ { 0x1110, "BeginProcAmdInitLate" },
+ { 0x1111, "EndProcAmdInitLate" },
+ { 0x1112, "BeginCreatSystemTable" },
+ { 0x1113, "EndCreatSystemTable" },
+ { 0x1114, "BeginDispatchCpuFeaturesLate" },
+ { 0x1115, "EndDispatchCpuFeaturesLate" },
+ { 0x1116, "BeginAmdCpuLate" },
+ { 0x1117, "EndAmdCpuLate" },
+ { 0x1118, "BeginGnbInitAtLate" },
+ { 0x1119, "EndGnbInitAtLate" },
+ { 0x111A, "BeginProcAmdInitMid" },
+ { 0x111B, "EndProcAmdInitMid" },
+ { 0x111E, "BeginInitMid" },
+ { 0x111F, "EndInitMid" },
+ { 0x1120, "BeginGnbInitAtMid" },
+ { 0x1121, "EndGnbInitAtMid" },
+ { 0x1122, "BeginProcAmdInitPost" },
+ { 0x1123, "EndProcAmdInitPost" },
+ { 0x1124, "BeginGnbInitAtPost" },
+ { 0x1125, "EndGnbInitAtPost" },
+ { 0x1126, "BeginAmdMemAuto" },
+ { 0x1127, "EndAmdMemAuto" },
+ { 0x1128, "BeginAmdCpuPost" },
+ { 0x1129, "EndAmdCpuPost" },
+ { 0x112A, "BeginGnbInitAtPostAfterDram" },
+ { 0x112B, "EndGnbInitAtPostAfterDram" },
+ { 0x112C, "BeginProcAmdInitReset" },
+ { 0x112D, "EndProcAmdInitReset" },
+ { 0x112E, "BeginInitReset" },
+ { 0x112F, "EndInitReset" },
+ { 0x1130, "BeginHtInitReset" },
+ { 0x1131, "EndHtInitReset" },
+ { 0x1132, "BeginProcAmdInitResume" },
+ { 0x1133, "EndProcAmdInitResume" },
+ { 0x1134, "BeginAmdMemS3Resume" },
+ { 0x1135, "EndAmdMemS3Resume" },
+ { 0x1136, "BeginDispatchCpuFeaturesS3Resume" },
+ { 0x1137, "EndDispatchCpuFeaturesS3Resume" },
+ { 0x1138, "BeginSetCoresTscFreqSel" },
+ { 0x1139, "EndSetCoresTscFreqSel" },
+ { 0x113A, "BeginMemFMctMemClr_Init" },
+ { 0x113B, "EndnMemFMctMemClr_Init" },
+ { 0x113C, "BeginMemBeforeMemDataInit" },
+ { 0x113D, "EndMemBeforeMemDataInit" },
+ { 0x113E, "BeginProcAmdMemAuto" },
+ { 0x113F, "EndProcAmdMemAuto" },
+ { 0x1140, "BeginMemMFlowC32" },
+ { 0x1141, "EndMemMFlowC32" },
+ { 0x1142, "BeginMemInitializeMCT" },
+ { 0x1143, "EndMemInitializeMCT" },
+ { 0x1144, "BeginMemSystemMemoryMapping" },
+ { 0x1145, "EndMemSystemMemoryMapping" },
+ { 0x1146, "BeginMemDramTraining" },
+ { 0x1147, "EndMemDramTraining" },
+ { 0x1148, "BeginMemOtherTiming" },
+ { 0x1149, "EndMemOtherTiming" },
+ { 0x114A, "BeginMemUMAMemTyping" },
+ { 0x114B, "EndMemUMAMemTyping" },
+ { 0x114C, "BeginMemMemClr" },
+ { 0x114D, "EndMemMemClr" },
+ { 0x114E, "BeginMemMFlowTN" },
+ { 0x114F, "EndMemMFlowTN" },
+ { 0x1150, "BeginAgesaHookBeforeDramInit" },
+ { 0x1151, "EndAgesaHookBeforeDramInit" },
+ { 0x1152, "BeginProcMemDramTraining" },
+ { 0x1153, "EndProcMemDramTraining" },
+ { 0x1154, "BeginGnbInitAtRtb" },
+ { 0x1155, "EndGnbInitAtRtb" },
+ { 0x1156, "BeginGnbLoadScsData" },
+ { 0x1157, "EndGnbLoadScsData" },
+ { 0x1158, "BeginGnbPcieTraining" },
+ { 0x1159, "EndGnbPcieTraining" },
+ { 0x115A, "BeginDispatchCpuFeaturesInitRtb" },
+ { 0x115B, "EndDispatchCpuFeaturesInitRtb" },
+ { 0x115C, "BeginAmdCpuEarly" },
+ { 0x115D, "EndAmdCpuEarly" },
+ { 0x115E, "BeginAmdGnbMidLate" },
+ { 0x115F, "EndAmdGnbMidLate" },
};
#endif
diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
index 986d6f8..0ce9dfb 100644
--- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
+++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
@@ -51,6 +51,8 @@
AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
AGESA_STATUS agesawrapper_fchs3laterestore(void);
+void *agesawrapper_allocateperfbuffer(void);
+
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID amd_initcpuio(void);
const void *agesawrapper_locate_module(const CHAR8 name[8]);
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 436bf8f..8f4368b 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -22,6 +22,7 @@
#include <delay.h>
#include <rules.h>
#include <rmodule.h>
+#include <stdlib.h>
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
@@ -315,6 +316,65 @@
return status;
}
+#if (ENV_RAMSTAGE)
+
+#define PERF_CANARY_VALUE 231
+
+static TP_Perf_STRUCT *PerfData;
+
+void *agesawrapper_allocateperfbuffer(void)
+{
+ if (PerfData) {
+ printk(BIOS_ERR,
+ "agesawrapper: perf pointer already allocated\n");
+ }
+
+ // Allocate an additional byte to use as a canary to detect a buffer
+ // overflow.
+ PerfData = malloc(sizeof(*PerfData) + 1);
+ ((uint8_t *)PerfData)[sizeof(*PerfData)] = PERF_CANARY_VALUE;
+
+ return PerfData;
+}
+
+/* Converts the AGESA perf data to cbmem timestamps. */
+static void commit_agesa_perf_data(void)
+{
+ if (PerfData == NULL) {
+ printk(BIOS_INFO, "agesawrapper: perf data not initialized\n");
+ return;
+ }
+
+ if (PerfData->Version != IDS_PERF_VERSION) {
+ printk(BIOS_ERR,
+ "agesawrapper: perf data malformed, expected version "
+ "%lx, but got %x\n",
+ IDS_PERF_VERSION, PerfData->Version);
+ return;
+ }
+
+ if (((uint8_t *)PerfData)[sizeof(*PerfData)] != PERF_CANARY_VALUE)
+ die("agesawrapper: perf data caused buffer overflow\n");
+
+ printk(BIOS_INFO,
+ "AGESA Performance Data: sig: %x, ver: %x, idx: %d, mhz: %d\n",
+ PerfData->Signature, PerfData->Version, PerfData->Index,
+ PerfData->TscInMhz);
+
+ for (int i = 0; i < PerfData->Index; ++i) {
+ TestPoint_TSC *tsc = &PerfData->TP[i];
+ if (tsc->Description == 0)
+ continue;
+
+ printk(BIOS_SPEW, "%llx:%x: %lld\n", tsc->Description,
+ tsc->LineInFile, tsc->StartTsc);
+ enum timestamp_id id = TS_AGESA_INTERNAL_START -
+ TP_BEGINPROCAMDINITEARLY +
+ tsc->Description;
+ timestamp_add(id, tsc->StartTsc / PerfData->TscInMhz);
+ }
+}
+
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
@@ -341,6 +401,8 @@
ASSERT(Status == AGESA_SUCCESS);
}
+ commit_agesa_perf_data();
+
DmiTable = LateParams->DmiTable;
AcpiPstate = LateParams->AcpiPState;
@@ -361,6 +423,17 @@
return Status;
}
+#else
+
+void *agesawrapper_allocateperfbuffer(void)
+{
+ // This will happen in S3 romstage because it happens in AmdInitResume.
+ printk(BIOS_NOTICE, "agesawrapper: perf pointer is not available\n");
+ return NULL;
+}
+
+#endif
+
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINTN Data,
VOID *ConfigPtr)
{
diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c
index fc3a88b..d0c1361 100644
--- a/src/soc/amd/common/block/pi/def_callouts.c
+++ b/src/soc/amd/common/block/pi/def_callouts.c
@@ -103,9 +103,14 @@
AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- IDS_NV_ITEM *IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+ IDS_CALLOUT_STRUCT *IdsCalloutData = (IDS_CALLOUT_STRUCT *) ConfigPtr;
+ IDS_NV_ITEM *IdsPtr = IdsCalloutData->IdsNvPtr;
if (Data == IDS_CALLOUT_INIT)
IdsPtr[0].IdsNvValue = IdsPtr[0].IdsNvId = 0xffff;
+ else if (Data == IDS_CALLOUT_GET_PERF_BUFFER)
+ IdsCalloutData->Reserved =
+ (UINTN)agesawrapper_allocateperfbuffer();
+
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h
new file mode 100644
index 0000000..2a65e18
--- /dev/null
+++ b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h
@@ -0,0 +1,65 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_LIB_H_
+#define _IDS_LIB_H_
+
+/// Data Structure of Parameters for TestPoint_TSC.
+typedef struct {
+ UINT32 LineInFile; ///< Line of current time counter
+ UINT64 Description; ///<Description ID
+ UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC
+} TestPoint_TSC;
+
+#define RESERVED_TP_NUMER 0x20
+#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER)
+/// Data Structure of Parameters for TP_Perf_STRUCT.
+typedef struct {
+ UINT32 Signature; ///< "PERF"
+ UINT32 Version; ///< version
+ UINT32 Index; ///< The Index of TP_Perf_STRUCT
+ UINT32 TscInMhz; ///< Tsc counter in 1 mhz
+ TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT
+} TP_Perf_STRUCT;
+
+#endif //_IDS_LIB_H_
+
diff --git a/src/vendorcode/amd/pi/00670F00/agesa_headers.h b/src/vendorcode/amd/pi/00670F00/agesa_headers.h
index a8deae5..fb17927 100644
--- a/src/vendorcode/amd/pi/00670F00/agesa_headers.h
+++ b/src/vendorcode/amd/pi/00670F00/agesa_headers.h
@@ -25,6 +25,7 @@
#include "Include/Ids.h"
#include "Include/PlatformMemoryConfiguration.h"
#include "Proc/Fch/FchPlatform.h"
+#include "Proc/IDS/IdsLib.h"
#include "Proc/Psp/PspBaseLib/PspBaseLib.h"
#pragma pack(pop)
#undef AGESA_HEADERS_ARE_WRAPPED
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If8399dd5d69d53ad41834b40d7f06d6b6e0093ad
Gerrit-Change-Number: 26220
Gerrit-PatchSet: 1
Gerrit-Owner: Raul Rangel <rrangel at chromium.org>
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