[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945/bootblock.c: Correct comment

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26207


Change subject: nb/intel/i945/bootblock.c: Correct comment
......................................................................

nb/intel/i945/bootblock.c: Correct comment

Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/intel/i945/bootblock.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26207/1

diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 4c3c90c..1b70df5 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -9,8 +9,8 @@
 
 	/*
 	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
-	 * to true. That way all subsequent non-explicit config accesses use
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true.
+	 * That way all subsequent non-explicit config accesses use
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the

-- 
To view, visit https://review.coreboot.org/26207
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Gerrit-Change-Number: 26207
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180509/da6fe0b9/attachment.html>