[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add common chip config block

Subrata Banik (Code Review) gerrit at coreboot.org
Wed May 9 11:58:56 CEST 2018 

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26189


Change subject: soc/intel/common/block: Add common chip config block
......................................................................

soc/intel/common/block: Add common chip config block

This patch to get soc specific chip structure for common code
block.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
A src/soc/intel/apollolake/include/soc/soc_chip.h
M src/soc/intel/cannonlake/Kconfig
A src/soc/intel/cannonlake/include/soc/soc_chip.h
A src/soc/intel/common/block/chip/Kconfig
A src/soc/intel/common/block/chip/Makefile.inc
A src/soc/intel/common/block/chip/chip.c
A src/soc/intel/common/block/include/intelblocks/chip.h
M src/soc/intel/skylake/Kconfig
A src/soc/intel/skylake/include/soc/soc_chip.h
10 files changed, 140 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26189/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 0f1f121..9f7af3b 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -70,6 +70,7 @@
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_DSP
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
diff --git a/src/soc/intel/apollolake/include/soc/soc_chip.h b/src/soc/intel/apollolake/include/soc/soc_chip.h
new file mode 100644
index 0000000..7672c49
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/soc_chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_SOC_CHIP_H_
+#define _SOC_APOLLOLAKE_SOC_CHIP_H_
+
+#include "chip.h"
+
+#endif /* _SOC_APOLLOLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ea399b8..098def5 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -45,6 +45,7 @@
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
 	select SOC_INTEL_COMMON_BLOCK_CSE
diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h
new file mode 100644
index 0000000..d378ab2
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_SOC_CHIP_H_
+#define _SOC_CANNONLAKE_SOC_CHIP_H_
+
+#include <chip.h>
+
+#endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig
new file mode 100644
index 0000000..273d088
--- /dev/null
+++ b/src/soc/intel/common/block/chip/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+	bool
+	help
+	  Intel Processor common soc/ chip configuration support
diff --git a/src/soc/intel/common/block/chip/Makefile.inc b/src/soc/intel/common/block/chip/Makefile.inc
new file mode 100644
index 0000000..425d5a2
--- /dev/null
+++ b/src/soc/intel/common/block/chip/Makefile.inc
@@ -0,0 +1,10 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG),y)
+
+bootblock-y += chip.c
+romstage-y += chip.c
+verstage-y += chip.c
+ramstage-y += chip.c
+smm-y += chip.c
+postcar-y += chip.c
+
+endif
diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c
new file mode 100644
index 0000000..1f49944
--- /dev/null
+++ b/src/soc/intel/common/block/chip/chip.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <intelblocks/chip.h>
+#include <soc/pci_devs.h>
+
+const config_t *chip_get_soc_structure(void)
+{
+	DEVTREE_CONST config_t *config;
+	int devfn = SA_DEVFN_ROOT;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+		       __func__);
+		return NULL;
+	}
+
+	config = dev->chip_info;
+
+	return config;
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
new file mode 100644
index 0000000..0549be9
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H
+#define SOC_INTEL_COMMON_BLOCK_CHIP_H
+
+#include <soc/soc_chip.h>
+
+/* This function to retrieve device tree structure */
+const config_t *chip_get_soc_structure(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 326b847..0a3d5a0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -56,6 +56,7 @@
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
 	select SOC_INTEL_COMMON_BLOCK_CSE
diff --git a/src/soc/intel/skylake/include/soc/soc_chip.h b/src/soc/intel/skylake/include/soc/soc_chip.h
new file mode 100644
index 0000000..e12120f
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/soc_chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SKYLAKE_SOC_CHIP_H_
+#define _SOC_SKYLAKE_SOC_CHIP_H_
+
+#include <chip.h>
+
+#endif /* _SOC_SKYLAKE_SOC_CHIP_H_ */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Gerrit-Change-Number: 26189
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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