[coreboot-gerrit] Change in coreboot[master]: soc/cavium: Add PCI support

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/25750 )

Change subject: soc/cavium: Add PCI support
......................................................................


Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/25750/1/src/soc/cavium/cn81xx/ecam0.c
File src/soc/cavium/cn81xx/ecam0.c:

https://review.coreboot.org/#/c/25750/1/src/soc/cavium/cn81xx/ecam0.c@20
PS1, Line 20: /*
            :  * Functions for accessing PCI configuration space with mmconf accesses
            :  */
            : #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK)	\
            : 			((void *)(((uintptr_t)ECAM_PF_BAR2 |\
            : 				   (((SEGBUS) & 0xFFF) << 20) |\
            : 				   (((DEVFN) & 0xFF) << 12) |\
            : 				   ((WHERE) & 0xFFF)) & ~MASK))
            : 
            : static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
            : 				       int where)
            : {
            : 	return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
            : }
            : 
            : static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
            : 					 int where)
            : {
            : 	return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
            : }
            : 
            : static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
            : 					 int where)
            : {
            : 	return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
            : }
            : 
            : static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
            : 				     int where, uint8_t value)
            : {
            : 	write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
            : }
            : 
            : static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
            : 				      int where, uint16_t value)
            : {
            : 	write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
            : }
            : 
            : static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
            : 				      int where, uint32_t value)
            : {
            : 	write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
            : }
            : 
            : static const struct pci_bus_operations pci_ops_ecam0_mmconf = {
            : 	.read8 = pci_mmconf_read_config8,
            : 	.read16 = pci_mmconf_read_config16,
            : 	.read32 = pci_mmconf_read_config32,
            : 	.write8 = pci_mmconf_write_config8,
            : 	.write16 = pci_mmconf_write_config16,
            : 	.write32 = pci_mmconf_write_config32,
            : };
Looks like a copy of `src/arch/x86/pci_ops_mmconf.c`. Obviously
not architecture specific. But copying it into a specific SoC
implementation makes the situation even worse.

The x86 implementation should just move to a generic place.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0
Gerrit-Change-Number: 25750
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Nico Huber <nico.h at gmx.de>
Gerrit-Comment-Date: Fri, 04 May 2018 13:39:52 +0000
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