[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception

[Julien Viard de Galbert (Code Review)]

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25434


Change subject: soc/intel/denverton_ns: Enable MC Exception
......................................................................

soc/intel/denverton_ns: Enable MC Exception

Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert at online.net>
---
M src/soc/intel/denverton_ns/cpu.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25434/1

diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 6c1298e..4434964 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -59,6 +59,12 @@
 	   of these banks are core vs package scope. For now every CPU clears
 	   every bank. */
 	mca_configure();
+
+	/* TODO install a fallback MC handler for each core in case OS does
+	   not provide one. Is it really needed ? */
+
+	/* Enable the machine check exception */
+	write_cr4(read_cr4() | CR4_MCE);
 }
 
 static void denverton_core_init(device_t cpu)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e
Gerrit-Change-Number: 25434
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
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