[coreboot-gerrit] Change in coreboot[master]: src/sb/intel/common/spi.c: Adapt and link in romstage

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/25414

to look at the new patch set (#2).

Change subject: src/sb/intel/common/spi.c: Adapt and link in romstage
......................................................................

src/sb/intel/common/spi.c: Adapt and link in romstage

Based on Nicola Corna's work.

This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the
console output to the SPI flash.

TESTED to still work in ramstage on x220 (correctly writes MRC CACHE),
the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the
common Intel SPI code (untested though).

Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/common/Makefile.inc
M src/southbridge/intel/common/spi.c
2 files changed, 101 insertions(+), 85 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25414/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Gerrit-Change-Number: 25414
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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