[coreboot-gerrit] Change in coreboot[master]: soc/cavium: Enable MMU

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25371


Change subject: soc/cavium: Enable MMU
......................................................................

soc/cavium: Enable MMU

* Configure and enable MMU.
* Use secure mem attribute as firmware is running in ARM TZ region.
* Increase TTB size to fit all page tables

Tested on Cavium SoC.

Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/mainboard/cavium/cn8100_sff_evb/romstage.c
M src/soc/cavium/cn81xx/Makefile.inc
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
A src/soc/cavium/cn81xx/include/soc/mmu.h
A src/soc/cavium/cn81xx/mmu.c
5 files changed, 70 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/25371/1

diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
index b466abb..4cf8f09 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
@@ -20,6 +20,7 @@
 #include <romstage_handoff.h>
 #include <soc/sdram.h>
 #include <soc/timer.h>
+#include <soc/mmu.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <program_loading.h>
@@ -32,6 +33,7 @@
 	exception_init();
 
 	sdram_init();
+	soc_mmu_init();
 
 	watchdog_poke(0);
 
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index d4fc57d..aac09a0 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -40,6 +40,8 @@
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
 romstage-y += l2c.c
 romstage-y += sdram.c
+romstage-y += mmu.c
+
 romstage-y += ../common/cbmem.c
 romstage-y += ../common/lame_string.c
 romstage-y += ../common/bdk/libbdk-arch/bdk-csr.c
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index cf43c51..fbbe665 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -40,8 +40,9 @@
 #if ENV_RAMSTAGE
 	STACK(0x2000000, 16K)
 	TIMESTAMP(0x2004000, 4K)
-	TTB(0x2005000, 44K)
-	RAMSTAGE(0x2010000, 512K)
 #endif
+	TTB(0x2005000, 108K)
+	RAMSTAGE(0x2020000, 512K)
+
 	POSTRAM_CBFS_CACHE(0x3000000, 16M)
 }
diff --git a/src/soc/cavium/cn81xx/include/soc/mmu.h b/src/soc/cavium/cn81xx/include/soc/mmu.h
new file mode 100644
index 0000000..9b811c3
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/mmu.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H
+#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H
+
+void soc_mmu_init(void);
+
+#endif  /* ! __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H */
diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c
new file mode 100644
index 0000000..7a77329
--- /dev/null
+++ b/src/soc/cavium/cn81xx/mmu.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <soc/addressmap.h>
+#include <soc/mmu.h>
+#include <soc/sdram.h>
+#include <arch/mmu.h>
+
+void soc_mmu_init(void)
+{
+	const unsigned long devmem = MA_DEV | MA_S | MA_RW;
+	const unsigned long secure_mem = MA_MEM | MA_S | MA_RW;
+
+	mmu_init();
+
+	/*
+	 * Need to use secure mem attribute, as firmware is running in ARM TZ
+	 * region.
+	 */
+	mmu_config_range((void *)_ttb, _ttb_size, secure_mem);
+	mmu_config_range((void *)_dram,
+			 ((uintptr_t)_dram + sdram_size_mb() * MiB),
+			 secure_mem);
+
+	mmu_config_range((void *)0x800000000000ULL, 0x80000000000ULL, devmem);
+
+	mmu_enable();
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Gerrit-Change-Number: 25371
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
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