[coreboot-gerrit] Change in coreboot[master]: drivers/pc80/tpm: Add some delay to tis_readresponse()

[Bill XIE (Code Review)]

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/25322


Change subject: drivers/pc80/tpm: Add some delay to tis_readresponse()
......................................................................

drivers/pc80/tpm: Add some delay to tis_readresponse()

Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1)
seem to need some delay between tis_wait_valid() and
tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0,
ending the loop immaturely with some bytes left unread, and fail to
pass the check below, causing the current command not finalized by
tis_command_ready(), and blocking any later tis_wait_ready().

Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5
Signed-off-by: Bill XIE <persmule at gmail.com>
---
M src/drivers/pc80/tpm/tis.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25322/1

diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 9802654..0c175dd 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -595,6 +595,12 @@
 		if (offset == expected_count)
 			break;	/* We got all we need */
 
+		/*
+		 * Certain TPMs seem to need some delay between tis_wait_valid()
+		 * and tis_has_valid_data(), or some race condition will occur.
+		 */
+		udelay(10);
+
 	} while (tis_has_valid_data(locality));
 
 	/* * Make sure we indeed read all there was. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5
Gerrit-Change-Number: 25322
Gerrit-PatchSet: 1
Gerrit-Owner: Bill XIE <persmule at gmail.com>
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